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Improve pre-RA-sched register pressure tracking for duplicate operands.

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This helps cases like 2008-07-19-movups-spills.ll, but doesn't have an obvious impact on benchmarks


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127347 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2011-03-09 19:12:43 +00:00
parent d1cba8727a
commit 4bbf4678e3
1 changed files with 5 additions and 1 deletions
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6
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
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@ -419,11 +419,15 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
}
if (!SU->addPred(dep) && !dep.isCtrl() && OpSU->NumRegDefsLeft > 0) {
if (!SU->addPred(dep) && !dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
// Multiple register uses are combined in the same SUnit. For example,
// we could have a set of glued nodes with all their defs consumed by
// another set of glued nodes. Register pressure tracking sees this as
// a single use, so to keep pressure balanced we reduce the defs.
//
// We can't tell (without more book-keeping) if this results from
// glued nodes or duplicate operands. As long as we don't reduce
// NumRegDefsLeft to zero, we handle the common cases well.
--OpSU->NumRegDefsLeft;
}
}