From 4bdcb61af33399d4e01fdf3c47ca1f1f5356e370 Mon Sep 17 00:00:00 2001 From: Duncan Sands Date: Wed, 2 Jul 2008 17:40:58 +0000 Subject: [PATCH] Add a new getMergeValues method that does not need to be passed the list of value types, and use this where appropriate. Inappropriate places are where the value type list is already known and may be long, in which case the existing method is more efficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53035 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 6 ++++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 15 +++++----- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 14 +++++++++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 30 ++++--------------- lib/Target/ARM/ARMISelLowering.cpp | 18 +++-------- lib/Target/CellSPU/SPUISelLowering.cpp | 21 ++++--------- lib/Target/PowerPC/PPCISelLowering.cpp | 12 ++++---- lib/Target/Sparc/SparcISelLowering.cpp | 6 ++-- lib/Target/X86/X86ISelLowering.cpp | 24 +++++++-------- 9 files changed, 63 insertions(+), 83 deletions(-) diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 994f66cc711..d0be1a8cc72 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -381,8 +381,14 @@ public: SDOperand Val, const Value* PtrVal, unsigned Alignment = 0); + /// getMergeValues - Create a MERGE_VALUES node from the given operands. + /// Allowed to return something different (and simpler) if Simplify is true. + SDOperand getMergeValues(SDOperandPtr Ops, unsigned NumOps, + bool Simplify = true); + /// getMergeValues - Create a MERGE_VALUES node from the given types and ops. /// Allowed to return something different (and simpler) if Simplify is true. + /// May be faster than the above version if VTs is known and NumOps is large. SDOperand getMergeValues(SDVTList VTs, SDOperandPtr Ops, unsigned NumOps, bool Simplify = true) { if (Simplify && NumOps == 1) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 196b2fcfb45..e5599b681b7 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -652,7 +652,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); SDOperand Ops[] = { Result, Chain }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + return DAG.getMergeValues(Ops, 2); } assert(LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type."); @@ -701,7 +701,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, Hi.getValue(1)); SDOperand Ops[] = { Result, TF }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + return DAG.getMergeValues(Ops, 2); } /// UnrollVectorOp - We know that the given vector has a legal type, however @@ -931,7 +931,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Fall Thru case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; - Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + Result = DAG.getMergeValues(Ops, 2); break; } } @@ -965,7 +965,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Fall Thru case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; - Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + Result = DAG.getMergeValues(Ops, 2); break; } } @@ -4728,16 +4728,15 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, } SDOperand Dummy; - Tmp1 = ExpandLibCall(LC1, - DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, + SDOperand Ops[2] = { LHS, RHS }; + Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val, false /*sign irrelevant*/, Dummy); Tmp2 = DAG.getConstant(0, MVT::i32); CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); if (LC2 != RTLIB::UNKNOWN_LIBCALL) { Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC); - LHS = ExpandLibCall(LC2, - DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, + LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val, false /*sign irrelevant*/, Dummy); Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index e23e0459e8b..c25b82aae73 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3074,6 +3074,20 @@ SDOperand SelectionDAG::getAtomic(unsigned Opcode, SDOperand Chain, return SDOperand(N, 0); } +/// getMergeValues - Create a MERGE_VALUES node from the given operands. +/// Allowed to return something different (and simpler) if Simplify is true. +SDOperand SelectionDAG::getMergeValues(SDOperandPtr Ops, unsigned NumOps, + bool Simplify) { + if (Simplify && NumOps == 1) + return Ops[0]; + + SmallVector VTs; + VTs.reserve(NumOps); + for (unsigned i = 0; i < NumOps; ++i) + VTs.push_back(Ops[i].getValueType()); + return getNode(ISD::MERGE_VALUES, getVTList(&VTs[0], NumOps), Ops, NumOps); +} + SDOperand SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, MVT VT, SDOperand Chain, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 12ba6ac3583..4f67dd4a227 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1158,17 +1158,13 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { if (isa(C) || isa(C)) { SmallVector Constants; - SmallVector ValueVTs; for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); OI != OE; ++OI) { SDNode *Val = getValue(*OI).Val; - for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) { + for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) Constants.push_back(SDOperand(Val, i)); - ValueVTs.push_back(Val->getValueType(i)); - } } - return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size()); } if (const ArrayType *ATy = dyn_cast(C->getType())) { @@ -1179,7 +1175,6 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { return SDOperand(); // empty array MVT EltVT = TLI.getValueType(ATy->getElementType()); SmallVector Constants(NumElts); - SmallVector ValueVTs(NumElts, EltVT); for (unsigned i = 0, e = NumElts; i != e; ++i) { if (isa(C)) Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); @@ -1188,8 +1183,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size()); } if (const StructType *STy = dyn_cast(C->getType())) { @@ -1199,10 +1193,8 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { if (NumElts == 0) return SDOperand(); // empty struct SmallVector Constants(NumElts); - SmallVector ValueVTs(NumElts); for (unsigned i = 0, e = NumElts; i != e; ++i) { MVT EltVT = TLI.getValueType(STy->getElementType(i)); - ValueVTs[i] = EltVT; if (isa(C)) Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); else if (EltVT.isFloatingPoint()) @@ -1210,8 +1202,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size()); } const VectorType *VecTy = cast(V->getType()); @@ -3771,10 +3762,7 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, ValueVT); Part += NumRegs; } - - if (ValueVTs.size() == 1) - return Values[0]; - + return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), &Values[0], ValueVTs.size()); } @@ -4944,13 +4932,7 @@ LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) { ComputeValueVTs(TLI, AI->getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); if (!AI->use_empty()) { - SmallVector LegalValueVTs(NumValues); - for (unsigned VI = 0; VI != NumValues; ++VI) - LegalValueVTs[VI] = Args[a + VI].getValueType(); - SDL.setValue(AI, - SDL.DAG.getMergeValues(SDL.DAG.getVTList(&LegalValueVTs[0], - NumValues), - &Args[a], NumValues)); + SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues)); // If this argument is live outside of the entry block, insert a copy from // whereever we got it to the vreg that other BB's will reference it as. DenseMap::iterator VMI=FuncInfo.ValueMap.find(AI); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 47abefeadc4..b19c1d7c7d3 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -587,10 +587,6 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { InFlag = Chain.getValue(1); } - std::vector NodeTys; - NodeTys.push_back(MVT::Other); // Returns a chain - NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. - std::vector Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -603,7 +599,9 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { if (InFlag.Val) Ops.push_back(InFlag); - Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); + // Returns a chain and a flag for retval copy to use. + Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + &Ops[0], Ops.size()); InFlag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, @@ -614,7 +612,6 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { InFlag = Chain.getValue(1); std::vector ResultVals; - NodeTys.clear(); // If the call has results, copy the values out of the ret val registers. switch (RetVT.getSimpleVT()) { @@ -629,33 +626,26 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, Chain.getValue(2)).getValue(1); ResultVals.push_back(Chain.getValue(0)); - NodeTys.push_back(MVT::i32); } - NodeTys.push_back(MVT::i32); break; case MVT::f32: Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Chain.getValue(0))); - NodeTys.push_back(MVT::f32); break; case MVT::f64: { SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); - NodeTys.push_back(MVT::f64); break; } } - NodeTys.push_back(MVT::Other); - if (ResultVals.empty()) return Chain; ResultVals.push_back(Chain); - SDOperand Res = DAG.getMergeValues(DAG.getVTList(&NodeTys[0], NodeTys.size()), - &ResultVals[0], ResultVals.size()); + SDOperand Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); return Res.getValue(Op.ResNo); } diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 1aae24ff1fd..403d751b4eb 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1177,10 +1177,6 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { InFlag = Chain.getValue(1); } - std::vector NodeTys; - NodeTys.push_back(MVT::Other); // Returns a chain - NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. - SmallVector Ops; unsigned CallOpc = SPUISD::CALL; @@ -1231,7 +1227,9 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (InFlag.Val) Ops.push_back(InFlag); - Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); + // Returns a chain and a flag for retval copy to use. + Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), + &Ops[0], Ops.size()); InFlag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, @@ -1243,7 +1241,6 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { SDOperand ResultVals[3]; unsigned NumResults = 0; - NodeTys.clear(); // If the call has results, copy the values out of the ret val registers. switch (Op.Val->getValueType(0).getSimpleVT()) { @@ -1257,19 +1254,16 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { Chain.getValue(2)).getValue(1); ResultVals[1] = Chain.getValue(0); NumResults = 2; - NodeTys.push_back(MVT::i32); } else { Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; } - NodeTys.push_back(MVT::i32); break; case MVT::i64: Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i64, InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; - NodeTys.push_back(MVT::i64); break; case MVT::f32: case MVT::f64: @@ -1277,7 +1271,6 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; - NodeTys.push_back(Op.Val->getValueType(0)); break; case MVT::v2f64: case MVT::v4f32: @@ -1288,20 +1281,16 @@ LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) { InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); NumResults = 1; - NodeTys.push_back(Op.Val->getValueType(0)); break; } - - NodeTys.push_back(MVT::Other); - + // If the function returns void, just return the chain. if (NumResults == 0) return Chain; // Otherwise, merge everything together with a MERGE_VALUES node. ResultVals[NumResults++] = Chain; - SDOperand Res = DAG.getMergeValues(DAG.getVTList(&NodeTys[0], NodeTys.size()), - ResultVals, NumResults); + SDOperand Res = DAG.getMergeValues(ResultVals, NumResults); return Res.getValue(Op.ResNo); } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 482ce63972b..4b2267d8122 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2752,7 +2752,7 @@ SDOperand PPCTargetLowering::LowerAtomicLOAD_ADD(SDOperand Op, SelectionDAG &DAG }; SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getMergeValues(OutOps, 2); } SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2794,7 +2794,7 @@ SDOperand PPCTargetLowering::LowerAtomicCMP_SWAP(SDOperand Op, SelectionDAG &DAG }; SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops3, 4); SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getMergeValues(OutOps, 2); } SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { @@ -2826,7 +2826,7 @@ SDOperand PPCTargetLowering::LowerAtomicSWAP(SDOperand Op, SelectionDAG &DAG) { }; SDOperand Store = DAG.getNode(PPCISD::STCX, MVT::Other, Ops2, 4); SDOperand OutOps[] = { Load, Store }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), OutOps, 2); + return DAG.getMergeValues(OutOps, 2); } /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when @@ -3130,7 +3130,7 @@ SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt); SDOperand OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2); + return DAG.getMergeValues(OutOps, 2); } SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { @@ -3158,7 +3158,7 @@ SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6); SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt); SDOperand OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2); + return DAG.getMergeValues(OutOps, 2); } SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { @@ -3186,7 +3186,7 @@ SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), Tmp4, Tmp6, ISD::SETLE); SDOperand OutOps[] = { OutLo, OutHi }; - return DAG.getMergeValues(DAG.getVTList(VT, VT), OutOps, 2); + return DAG.getMergeValues(OutOps, 2); } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index cd645bfaeae..2f4181335bb 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -446,7 +446,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { } ResultVals.push_back(Chain); - + // Merge everything together with a MERGE_VALUES node. return DAG.getMergeValues(Op.Val->getVTList(), &ResultVals[0], ResultVals.size()); @@ -829,7 +829,7 @@ static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG) { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), V.getValue(1) }; - return DAG.getMergeValues(DAG.getVTList(MVT::f64, MVT::Other), Ops, 2); + return DAG.getMergeValues(Ops, 2); } static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) { @@ -846,7 +846,7 @@ static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG) { SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, DAG.getConstant(96, MVT::i32)); SDOperand Ops[2] = { NewVal, Chain }; - return DAG.getMergeValues(DAG.getVTList(MVT::i32, MVT::Other), Ops, 2); + return DAG.getMergeValues(Ops, 2); } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 2fbc25c96d4..9b57f3ac43a 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -978,7 +978,7 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, ResultVals.push_back(Val); } - + // Merge everything together with a MERGE_VALUES node. ResultVals.push_back(Chain); return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0], @@ -4382,7 +4382,7 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) { } SDOperand Ops[2] = { Lo, Hi }; - return DAG.getMergeValues(DAG.getVTList(VT, VT), Ops, 2); + return DAG.getMergeValues(Ops, 2); } SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { @@ -4516,9 +4516,10 @@ SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) { // Return a load from the stack slot. SDOperand Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0); - // Use a MERGE_VALUES node to drop the chain result value. - return DAG.getMergeValues(DAG.getVTList(VT), &Res, 1, - false /* Require a node with one-result */).Val; + // Use MERGE_VALUES to drop the chain result value and get a node with one + // result. This requires turning off getMergeValues simplification, since + // otherwise it will give us Res back. + return DAG.getMergeValues(&Res, 1, false).Val; } SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) { @@ -4816,7 +4817,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op, Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1); SDOperand Ops1[2] = { Chain.getValue(0), Chain }; - return DAG.getMergeValues(DAG.getVTList(SPTy, MVT::Other), Ops1, 2); + return DAG.getMergeValues(Ops1, 2); } SDOperand @@ -5047,8 +5048,7 @@ SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1) }; - Tys = DAG.getVTList(MVT::i64, MVT::Other); - return DAG.getMergeValues(Tys, Ops, 2).Val; + return DAG.getMergeValues(Ops, 2).Val; } SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)); @@ -5060,7 +5060,7 @@ SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){ // Use a MERGE_VALUES to return the value and chain. Ops[1] = edx.getValue(1); - return DAG.getMergeValues(DAG.getVTList(MVT::i64, MVT::Other), Ops, 2).Val; + return DAG.getMergeValues(Ops, 2).Val; } SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) { @@ -5441,7 +5441,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) }; - return DAG.getMergeValues(Op.Val->getVTList(), Ops, 2); + return DAG.getMergeValues(Ops, 2); } else { const Function *Func = cast(cast(Op.getOperand(5))->getValue()); @@ -5509,7 +5509,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op, SDOperand Ops[] = { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) }; - return DAG.getMergeValues(Op.Val->getVTList(), Ops, 2); + return DAG.getMergeValues(Ops, 2); } } @@ -5697,7 +5697,7 @@ SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op, SelectionDAG &DAG) SDOperand OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; SDOperand ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); SDOperand Vals[2] = { ResultVal, cpOutH.getValue(1) }; - return DAG.getMergeValues(DAG.getVTList(MVT::i64, MVT::Other), Vals, 2).Val; + return DAG.getMergeValues(Vals, 2).Val; } SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op, SelectionDAG &DAG) {