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Refactor some duplicated code into helper functions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-03-18 02:53:34 +00:00
parent 4d0cdca6f6
commit 4bef961baf
2 changed files with 64 additions and 231 deletions
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288
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -1739,242 +1739,68 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
return false;
}
static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg,
bool isCmp) {
MCInst TmpInst;
TmpInst.setOpcode(Opcode);
if (!isCmp)
TmpInst.addOperand(MCOperand::CreateReg(Reg));
TmpInst.addOperand(MCOperand::CreateReg(Reg));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
static bool convert16i16to16ri8(MCInst &Inst, unsigned Opcode,
bool isCmp = false) {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
return false;
return convertToSExti8(Inst, Opcode, X86::AX, isCmp);
}
static bool convert32i32to32ri8(MCInst &Inst, unsigned Opcode,
bool isCmp = false) {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
return false;
return convertToSExti8(Inst, Opcode, X86::EAX, isCmp);
}
static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
bool isCmp = false) {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
return false;
return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
}
bool X86AsmParser::
processInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
switch (Inst.getOpcode()) {
default: return false;
case X86::AND16i16: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::AND16ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::AND32i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::AND32ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::AND64i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::AND64ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::XOR16i16: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::XOR16ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::XOR32i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::XOR32ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::XOR64i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::XOR64ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::OR16i16: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::OR16ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::OR32i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::OR32ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::OR64i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::OR64ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::CMP16i16: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::CMP16ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::CMP32i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::CMP32ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::CMP64i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::CMP64ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::ADD16i16: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::ADD16ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::ADD32i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::ADD32ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::ADD64i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::ADD64ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::SUB16i16: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::SUB16ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::SUB32i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::SUB32ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::SUB64i32: {
if (!Inst.getOperand(0).isImm() ||
!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
return false;
MCInst TmpInst;
TmpInst.setOpcode(X86::SUB64ri8);
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
TmpInst.addOperand(Inst.getOperand(0));
Inst = TmpInst;
return true;
}
case X86::AND16i16: return convert16i16to16ri8(Inst, X86::AND16ri8);
case X86::AND32i32: return convert32i32to32ri8(Inst, X86::AND32ri8);
case X86::AND64i32: return convert64i32to64ri8(Inst, X86::AND64ri8);
case X86::XOR16i16: return convert16i16to16ri8(Inst, X86::XOR16ri8);
case X86::XOR32i32: return convert32i32to32ri8(Inst, X86::XOR32ri8);
case X86::XOR64i32: return convert64i32to64ri8(Inst, X86::XOR64ri8);
case X86::OR16i16: return convert16i16to16ri8(Inst, X86::OR16ri8);
case X86::OR32i32: return convert32i32to32ri8(Inst, X86::OR32ri8);
case X86::OR64i32: return convert64i32to64ri8(Inst, X86::OR64ri8);
case X86::CMP16i16: return convert16i16to16ri8(Inst, X86::CMP16ri8, true);
case X86::CMP32i32: return convert32i32to32ri8(Inst, X86::CMP32ri8, true);
case X86::CMP64i32: return convert64i32to64ri8(Inst, X86::CMP64ri8, true);
case X86::ADD16i16: return convert16i16to16ri8(Inst, X86::ADD16ri8);
case X86::ADD32i32: return convert32i32to32ri8(Inst, X86::ADD32ri8);
case X86::ADD64i32: return convert64i32to64ri8(Inst, X86::ADD64ri8);
case X86::SUB16i16: return convert16i16to16ri8(Inst, X86::SUB16ri8);
case X86::SUB32i32: return convert32i32to32ri8(Inst, X86::SUB32ri8);
case X86::SUB64i32: return convert64i32to64ri8(Inst, X86::SUB64ri8);
}
}

7
test/MC/X86/intel-syntax-encoding.s
View File

@ -31,6 +31,13 @@
// CHECK: encoding: [0x48,0x83,0xc0,0xf4]
add rax, -12
// CHECK: encoding: [0x66,0x83,0xf8,0xf4]
cmp ax, -12
// CHECK: encoding: [0x83,0xf8,0xf4]
cmp eax, -12
// CHECK: encoding: [0x48,0x83,0xf8,0xf4]
cmp rax, -12
LBB0_3:
// CHECK: encoding: [0xeb,A]
jmp LBB0_3