From 4c6b3d35bb1cbbdd4c9fa9744df0d1fa0e09216f Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Fri, 17 Dec 2010 23:06:46 +0000 Subject: [PATCH] Combine several vector-related DAGCombiner tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122101 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../ARM/2010-05-17-DAGCombineAssert.ll | 17 ----- .../CodeGen/ARM/2010-06-28-DAGCombineUndef.ll | 10 --- .../CodeGen/ARM/2010-09-17-vmovrrd-combine.ll | 26 -------- .../ARM/2010-11-17-DAGCombineShiftBug.ll | 8 --- test/CodeGen/ARM/vector-DAGCombine.ll | 63 +++++++++++++++++++ 5 files changed, 63 insertions(+), 61 deletions(-) delete mode 100644 test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll delete mode 100644 test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll delete mode 100644 test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll delete mode 100644 test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll create mode 100644 test/CodeGen/ARM/vector-DAGCombine.ll diff --git a/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll b/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll deleted file mode 100644 index 2a4bbd1d8cc..00000000000 --- a/test/CodeGen/ARM/2010-05-17-DAGCombineAssert.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 -; PR7158 - -define arm_aapcs_vfpcc i32 @main() nounwind { -bb.nph55.bb.nph55.split_crit_edge: - br label %bb3 - -bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge - br i1 undef, label %bb.i19, label %bb3 - -bb.i19: ; preds = %bb.i19, %bb3 - %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3] - %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1] - %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0] - %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0] - br label %bb.i19 -} diff --git a/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll deleted file mode 100644 index ad2810b5bb9..00000000000 --- a/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: llc < %s -march=arm -mattr=+neon - -define void @main() nounwind { -entry: - store <2 x i64> undef, <2 x i64>* undef, align 16 - %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] - %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] - store <16 x i8> %1, <16 x i8>* undef, align 16 - ret void -} diff --git a/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll b/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll deleted file mode 100644 index a210986c0b7..00000000000 --- a/test/CodeGen/ARM/2010-09-17-vmovrrd-combine.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is -; converted back to be used as a vector type. - -; CHECK: test: -define <4 x i32> @test() nounwind { -entry: - br i1 undef, label %bb1, label %bb2 - -bb1: - %0 = bitcast <2 x i64> zeroinitializer to <2 x double> - %1 = extractelement <2 x double> %0, i32 0 - %2 = bitcast double %1 to i64 - %3 = insertelement <1 x i64> undef, i64 %2, i32 0 -; CHECK-NOT: vmov s -; CHECK: vext.8 - %4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> - %tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8> - %5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> - %tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32> - br i1 undef, label %bb2, label %bb1 - -bb2: - %result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ] - ret <4 x i32> %result -} diff --git a/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll b/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll deleted file mode 100644 index b9cf3520235..00000000000 --- a/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: llc < %s -march=arm -mattr=+neon -define void @lshrIllegalType(<8 x i32>* %A) nounwind { - %tmp1 = load <8 x i32>* %A - %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> - store <8 x i32> %tmp2, <8 x i32>* %A - ret void -} - diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll new file mode 100644 index 00000000000..fa08c1f69b2 --- /dev/null +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -0,0 +1,63 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +; PR7158 +define arm_aapcs_vfpcc i32 @test_pr7158() nounwind { +bb.nph55.bb.nph55.split_crit_edge: + br label %bb3 + +bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge + br i1 undef, label %bb.i19, label %bb3 + +bb.i19: ; preds = %bb.i19, %bb3 + %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3] + %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1] + %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0] + %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0] + br label %bb.i19 +} + +; Check that the DAG combiner does not arbitrarily modify BUILD_VECTORs +; after legalization. +define void @test_illegal_build_vector() nounwind { +entry: + store <2 x i64> undef, <2 x i64>* undef, align 16 + %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1] + %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1] + store <16 x i8> %1, <16 x i8>* undef, align 16 + ret void +} + +; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is +; converted back to be used as a vector type. +; CHECK: test_vmovrrd_combine +define <4 x i32> @test_vmovrrd_combine() nounwind { +entry: + br i1 undef, label %bb1, label %bb2 + +bb1: + %0 = bitcast <2 x i64> zeroinitializer to <2 x double> + %1 = extractelement <2 x double> %0, i32 0 + %2 = bitcast double %1 to i64 + %3 = insertelement <1 x i64> undef, i64 %2, i32 0 +; CHECK-NOT: vmov s +; CHECK: vext.8 + %4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> + %tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8> + %5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> + %tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32> + br i1 undef, label %bb2, label %bb1 + +bb2: + %result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ] + ret <4 x i32> %result +} + +; Test trying to do a ShiftCombine on illegal types. +; The vector should be split first. +define void @lshrIllegalType(<8 x i32>* %A) nounwind { + %tmp1 = load <8 x i32>* %A + %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> + store <8 x i32> %tmp2, <8 x i32>* %A + ret void +} +