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This reverts r155000.

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The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.

VFP instructions on v8/AArch32 share the same encoding space as cdp2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joey Gouly 2013-06-20 17:42:36 +00:00
parent d69d9f20bc
commit 4cbbbf49b6
4 changed files with 7 additions and 10 deletions
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7
lib/Target/ARM/ARMInstrInfo.td
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@ -1007,11 +1007,6 @@ def p_imm : Operand<i32> {
let DecoderMethod = "DecodeCoprocessor";
}
def pf_imm : Operand<i32> {
let PrintMethod = "printPImmediate";
let ParserMatchClass = CoprocNumAsmOperand;
}
def CoprocRegAsmOperand : AsmOperandClass {
let Name = "CoprocReg";
let ParserMethod = "parseCoprocRegOperand";
@ -4447,7 +4442,7 @@ def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
let Inst{23-20} = opc1;
}
def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,

2
test/MC/ARM/basic-arm-instructions.s
View File

@ -459,9 +459,11 @@ Lforward:
@------------------------------------------------------------------------------
cdp p7, #1, c1, c1, c1, #4
cdp2 p7, #1, c1, c1, c1, #4
cdp2 p10, #0, c6, c12, c0, #7
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
@ CHECK: cdp2 p10, #0, c6, c12, c0, #7 @ encoding: [0xe0,0x6a,0x0c,0xfe]
@------------------------------------------------------------------------------

4
test/MC/Disassembler/ARM/arm-tests.txt
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@ -362,7 +362,3 @@
# CHECK: ldmgt sp!, {r9}
0x00 0x02 0xbd 0xc8
# CHECK: cdp2 p10, #0, c6, c12, c0, #7
0xe0 0x6a 0x0c 0xfe

4
test/MC/Disassembler/ARM/invalid-CDP2-arm.txt Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm 2>&1 | FileCheck %s
# CHECK: invalid instruction encoding
0xe0 0x6a 0x0c 0xfe