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Implement a method for inline asm support

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25660 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-01-26 20:37:03 +00:00
parent 8211e82e40
commit 4ccb070f15
1 changed files with 17 additions and 0 deletions
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17
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@@ -13,7 +13,9 @@
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/ADT/StringExtras.h"
using namespace llvm; using namespace llvm;
TargetLowering::TargetLowering(TargetMachine &tm) TargetLowering::TargetLowering(TargetMachine &tm)
@@ -132,3 +134,18 @@ bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
uint64_t Mask) const { uint64_t Mask) const {
return false; return false;
} }
std::vector<unsigned> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint) const {
// Scan to see if this constraint is a register name.
const MRegisterInfo *RI = TM.getRegisterInfo();
for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) {
if (const char *Name = RI->get(i).Name)
if (StringsEqualNoCase(Constraint, Name))
return std::vector<unsigned>(1, i);
}
// Not a physreg, must not be a register reference or something.
return std::vector<unsigned>();
}