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R600/SI: remove SI_vs_load_buffer_index
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176625 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -60,8 +60,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::ADD, MVT::i64, Legal);
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setOperationAction(ISD::ADD, MVT::i32, Legal);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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@ -241,18 +239,6 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntrinsicID =
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cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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EVT VT = Op.getValueType();
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switch (IntrinsicID) {
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case AMDGPUIntrinsic::SI_vs_load_buffer_index:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR0, VT);
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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}
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break;
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}
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}
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return SDValue();
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}
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@ -18,7 +18,6 @@ let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
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/* XXX: We may need a seperate intrinsic here for loading integer values */
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_i64_ty, llvm_i32_ty], []>;
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def int_SI_vs_load_buffer_index : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>;
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_i16_ty, llvm_i32_ty], [IntrReadMem]> ;
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def int_SI_wqm : Intrinsic <[], [], []>;
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