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Make the disassembler tables const so they end up in read-only memory.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117206 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2010-10-23 09:10:44 +00:00
parent c527407010
commit 4d1dca92bd
5 changed files with 20 additions and 24 deletions
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15
lib/Target/X86/Disassembler/X86Disassembler.cpp
View File

@ -157,9 +157,8 @@ static void translateRegister(MCInst &mcInst, Reg reg) {
/// @param immediate - The immediate value to append.
/// @param operand - The operand, as stored in the descriptor table.
/// @param insn - The internal instruction.
static void translateImmediate(MCInst &mcInst,
uint64_t immediate,
OperandSpecifier &operand,
static void translateImmediate(MCInst &mcInst, uint64_t immediate,
const OperandSpecifier &operand,
InternalInstruction &insn) {
// Sign-extend the immediate if necessary.
@ -392,9 +391,8 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) {
/// @param insn - The instruction to extract Mod, R/M, and SIB fields
/// from.
/// @return - 0 on success; nonzero otherwise
static bool translateRM(MCInst &mcInst,
OperandSpecifier &operand,
InternalInstruction &insn) {
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
InternalInstruction &insn) {
switch (operand.type) {
default:
debug("Unexpected type for a R/M operand");
@ -461,9 +459,8 @@ static bool translateFPRegister(MCInst &mcInst,
/// @param operand - The operand, as stored in the descriptor table.
/// @param insn - The internal instruction.
/// @return - false on success; true otherwise.
static bool translateOperand(MCInst &mcInst,
OperandSpecifier &operand,
InternalInstruction &insn) {
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
InternalInstruction &insn) {
switch (operand.encoding) {
default:
debug("Unhandled operand encoding during translation");

2
lib/Target/X86/Disassembler/X86Disassembler.h
View File

@ -78,7 +78,7 @@
const char* name;
#define INSTRUCTION_IDS \
InstrUID* instructionIDs;
const InstrUID *instructionIDs;
#include "X86DisassemblerDecoderCommon.h"

14
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
View File

@ -97,7 +97,7 @@ static InstrUID decode(OpcodeType type,
InstructionContext insnContext,
uint8_t opcode,
uint8_t modRM) {
struct ModRMDecision* dec;
const struct ModRMDecision* dec;
switch (type) {
default:
@ -141,7 +141,7 @@ static InstrUID decode(OpcodeType type,
* decode(); specifierForUID will not check bounds.
* @return - A pointer to the specification for that instruction.
*/
static struct InstructionSpecifier* specifierForUID(InstrUID uid) {
static const struct InstructionSpecifier *specifierForUID(InstrUID uid) {
return &INSTRUCTIONS_SYM[uid];
}
@ -626,9 +626,9 @@ static int getID(struct InternalInstruction* insn) {
* instead of F2 changes a 32 to a 64, we adopt the new encoding.
*/
struct InstructionSpecifier* spec;
const struct InstructionSpecifier *spec;
uint16_t instructionIDWithREXw;
struct InstructionSpecifier* specWithREXw;
const struct InstructionSpecifier *specWithREXw;
spec = specifierForUID(instructionID);
@ -666,9 +666,9 @@ static int getID(struct InternalInstruction* insn) {
* in the right place we check if there's a 16-bit operation.
*/
struct InstructionSpecifier* spec;
const struct InstructionSpecifier *spec;
uint16_t instructionIDWithOpsize;
struct InstructionSpecifier* specWithOpsize;
const struct InstructionSpecifier *specWithOpsize;
spec = specifierForUID(instructionID);
@ -1061,7 +1061,7 @@ GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
* invalid for its class.
*/
static int fixupReg(struct InternalInstruction *insn,
struct OperandSpecifier *op) {
const struct OperandSpecifier *op) {
uint8_t valid;
dbgprintf(insn, "fixupReg()");

4
lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
View File

@ -24,7 +24,7 @@ extern "C" {
const char* name;
#define INSTRUCTION_IDS \
InstrUID* instructionIDs;
const InstrUID *instructionIDs;
#include "X86DisassemblerDecoderCommon.h"
@ -423,7 +423,7 @@ struct InternalInstruction {
/* The instruction ID, extracted from the decode table */
uint16_t instructionID;
/* The specifier for the instruction, from the instruction info table */
struct InstructionSpecifier* spec;
const struct InstructionSpecifier *spec;
/* state for additional bytes, consumed during operand decode. Pattern:
consumed___ indicates that the byte was already consumed and does not

9
utils/TableGen/X86DisassemblerTables.cpp
View File

@ -275,7 +275,7 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
return;
}
o1.indent(i1) << "static InstrUID modRMTable" << thisTableNumber;
o1.indent(i1) << "static const InstrUID modRMTable" << thisTableNumber;
switch (dt) {
default:
@ -365,7 +365,7 @@ void DisassemblerTables::emitContextDecision(
uint32_t &i2,
ContextDecision &decision,
const char* name) const {
o2.indent(i2) << "static struct ContextDecision " << name << " = {\n";
o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
i2++;
o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
i2++;
@ -392,9 +392,8 @@ void DisassemblerTables::emitContextDecision(
void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
const {
o.indent(i * 2) << "static struct InstructionSpecifier " INSTRUCTIONS_STR "[";
o << InstructionSpecifiers.size();
o << "] = {" << "\n";
o.indent(i * 2) << "static const struct InstructionSpecifier ";
o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
i++;