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Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Barton 2012-04-27 08:42:59 +00:00
parent d213ee7643
commit 4d2f077df1
3 changed files with 7 additions and 14 deletions
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7
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -7214,9 +7214,7 @@ processInstruction(MCInst &Inst,
// The mask bits for all but the first condition are represented as
// the low bit of the condition code value implies 't'. We currently
// always have 1 implies 't', so XOR toggle the bits if the low bit
// of the condition code is zero. The encoding also expects the low
// bit of the condition to be encoded as bit 4 of the mask operand,
// so mask that in if needed
// of the condition code is zero.
MCOperand &MO = Inst.getOperand(1);
unsigned Mask = MO.getImm();
unsigned OrigMask = Mask;
@ -7225,8 +7223,7 @@ processInstruction(MCInst &Inst,
assert(Mask && TZ <= 3 && "illegal IT mask value!");
for (unsigned i = 3; i != TZ; --i)
Mask ^= 1 << i;
} else
Mask |= 0x10;
}
MO.setImm(Mask);
// Set up the IT block state according to the IT instruction we just

11
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -63,7 +63,7 @@ namespace {
// fields in the IT instruction encoding.
void setITState(char Firstcond, char Mask) {
// (3 - the number of trailing zeros) is the number of then / else.
unsigned CondBit0 = Mask >> 4 & 1;
unsigned CondBit0 = Firstcond & 1;
unsigned NumTZ = CountTrailingZeros_32(Mask);
unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
assert(NumTZ <= 3 && "Invalid IT mask!");
@ -4217,19 +4217,14 @@ static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned pred = fieldFromInstruction16(Insn, 4, 4);
// The InstPrinter needs to have the low bit of the predicate in
// the mask operand to be able to print it properly.
unsigned mask = fieldFromInstruction16(Insn, 0, 5);
unsigned mask = fieldFromInstruction16(Insn, 0, 4);
if (pred == 0xF) {
pred = 0xE;
S = MCDisassembler::SoftFail;
}
if ((mask & 0xF) == 0) {
// Preserve the high bit of the mask, which is the low bit of
// the predicate.
mask &= 0x10;
if (mask == 0x0) {
mask |= 0x8;
S = MCDisassembler::SoftFail;
}

3
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -754,7 +754,8 @@ void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
// (3 - the number of trailing zeros) is the number of then / else.
unsigned Mask = MI->getOperand(OpNum).getImm();
unsigned CondBit0 = Mask >> 4 & 1;
unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
unsigned CondBit0 = Firstcond & 1;
unsigned NumTZ = CountTrailingZeros_32(Mask);
assert(NumTZ <= 3 && "Invalid IT mask!");
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {