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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30486 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-09-19 16:41:40 +00:00
parent 71f3b94fa8
commit 4d4c021758
1 changed files with 21 additions and 18 deletions
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39
lib/Target/ARM/ARMMul.cpp
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@ -1,4 +1,4 @@
//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
//===-- ARMMul.cpp - Define TargetMachine for A5CRM -----------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -8,6 +8,7 @@
//
//===----------------------------------------------------------------------===//
//
// Modify the ARM multiplication instructions so that Rd and Rm are distinct
//
//===----------------------------------------------------------------------===//
@ -39,25 +40,27 @@ bool FixMul::runOnMachineFunction(MachineFunction &MF) {
MachineInstr *MI = I;
if (MI->getOpcode() == ARM::MUL) {
MachineOperand &RdOp = MI->getOperand(0);
MachineOperand &RmOp = MI->getOperand(1);
MachineOperand &RsOp = MI->getOperand(2);
MachineOperand &RdOp = MI->getOperand(0);
MachineOperand &RmOp = MI->getOperand(1);
MachineOperand &RsOp = MI->getOperand(2);
unsigned Rd = RdOp.getReg();
unsigned Rm = RmOp.getReg();
unsigned Rs = RsOp.getReg();
unsigned Rd = RdOp.getReg();
unsigned Rm = RmOp.getReg();
unsigned Rs = RsOp.getReg();
if(Rd == Rm) {
Changed = true;
if (Rd != Rs) {
RmOp.setReg(Rs);
RsOp.setReg(Rm);
} else {
BuildMI(MBB, I, ARM::MOV, 3, ARM::R12).addReg(Rm).addImm(0)
.addImm(ARMShift::LSL);
RmOp.setReg(ARM::R12);
}
}
if(Rd == Rm) {
Changed = true;
if (Rd != Rs) {
//Rd and Rm must be distinct, but Rd can be equal to Rs.
//Swap Rs and Rm
RmOp.setReg(Rs);
RsOp.setReg(Rm);
} else {
BuildMI(MBB, I, ARM::MOV, 3, ARM::R12).addReg(Rm).addImm(0)
.addImm(ARMShift::LSL);
RmOp.setReg(ARM::R12);
}
}
}
}
}