6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-13 09:33:50 +00:00
Code Issues Projects Releases Wiki Activity

Don't reserve R2 on Darwin/PPC

Browse Source 
Now that only the register-scavenger version of the CR spilling code remains,
we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in
any case where the System V ABI uses it (R0 is special architecturally, and so
is reserved under all common ABIs).

A few test cases needed to be updated to reflect the register-allocation changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-12 15:18:14 +00:00
parent 7285e8d98c
commit 4d53e7798c
7 changed files with 36 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -121,12 +121,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(PPC::R2); // System-reserved register
Reserved.set(PPC::R13); // Small Data Area pointer register
}
// Reserve R2 on Darwin to hack around the problem of save/restore of CR
// when the stack frame is too big to address directly; we need two regs.
// This is a hack.
if (Subtarget.isDarwinABI()) {
Reserved.set(PPC::R2);
}
// On PPC64, r13 is the thread pointer. Never allocate this register.
// Note that this is over conservative, as it also prevents allocation of R31
@ -144,12 +138,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
if (Subtarget.isSVR4ABI()) {
Reserved.set(PPC::X2);
}
// Reserve X2 on Darwin to hack around the problem of save/restore of CR
// when the stack frame is too big to address directly; we need two regs.
// This is a hack.
if (Subtarget.isDarwinABI()) {
Reserved.set(PPC::X2);
}
}
if (PPCFI->needsFP(MF))
@ -334,8 +322,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
(void) RS;
bool LP64 = Subtarget.isPPC64();
unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
(LP64 ? PPC::X0 : PPC::R0);
unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
unsigned SrcReg = MI.getOperand(0).getReg();
// We need to store the CR in the low 4-bits of the saved value. First, issue
@ -377,8 +364,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
(void) RS;
bool LP64 = Subtarget.isPPC64();
unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) :
(LP64 ? PPC::X0 : PPC::R0);
unsigned Reg = LP64 ? PPC::X0 : PPC::R0;
unsigned DestReg = MI.getOperand(0).getReg();
assert(MI.definesRegister(DestReg) &&
"RESTORE_CR does not define its destination");

4
test/CodeGen/PowerPC/2009-08-17-inline-asm-addr-mode-breakage.ll
View File

@ -10,8 +10,8 @@ target triple = "powerpc-apple-darwin10.0"
define void @foo(i32 %y) nounwind ssp {
entry:
; CHECK: foo
; CHECK: add r3
; CHECK: 0(r3)
; CHECK: add r2
; CHECK: 0(r2)
%y_addr = alloca i32 ; <i32*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i32 %y, i32* %y_addr

30
test/CodeGen/PowerPC/2010-02-12-saveCR.ll
View File

@ -6,17 +6,17 @@ target triple = "powerpc-apple-darwin9.6"
define void @foo() nounwind {
entry:
;CHECK: mfcr r2
;CHECK: lis r3, 1
;CHECK: rlwinm r2, r2, 8, 0, 31
;CHECK: ori r3, r3, 34524
;CHECK: stwx r2, r1, r3
;CHECK: mfcr r0
;CHECK: lis r2, 1
;CHECK: rlwinm r0, r0, 8, 0, 31
;CHECK: ori r2, r2, 34524
;CHECK: stwx r0, r1, r2
; Make sure that the register scavenger returns the same temporary register.
;CHECK: mfcr r2
;CHECK: lis r3, 1
;CHECK: rlwinm r2, r2, 12, 0, 31
;CHECK: ori r3, r3, 34520
;CHECK: stwx r2, r1, r3
;CHECK: lis r2, 1
;CHECK: mfcr r0
;CHECK: ori r2, r2, 34520
;CHECK: rlwinm r0, r0, 12, 0, 31
;CHECK: stwx r0, r1, r2
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
@ -25,11 +25,11 @@ entry:
br label %return
return: ; preds = %entry
;CHECK: lis r3, 1
;CHECK: ori r3, r3, 34524
;CHECK: lwzx r2, r1, r3
;CHECK: rlwinm r2, r2, 24, 0, 31
;CHECK: mtcrf 32, r2
;CHECK: lis r2, 1
;CHECK: ori r2, r2, 34524
;CHECK: lwzx r0, r1, r2
;CHECK: rlwinm r0, r0, 24, 0, 31
;CHECK: mtcrf 32, r0
ret void
}

4
test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
View File

@ -18,8 +18,8 @@ entry:
; CHECK: _g:
; CHECK: mflr r0
; CHECK: stw r0, 8(r1)
; CHECK: lwz r3, 0(r1)
; CHECK: lwz r3, 8(r3)
; CHECK: lwz r2, 0(r1)
; CHECK: lwz r3, 8(r2)
%0 = tail call i8* @llvm.returnaddress(i32 1) ; <i8*> [#uses=1]
ret i8* %0
}

2
test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
View File

@ -7,7 +7,7 @@ define i32 @main() nounwind {
entry:
; Make sure we're generating references using the red zone
; CHECK: main:
; CHECK: stw r3, -12(r1)
; CHECK: stw r2, -12(r1)
%retval = alloca i32
%0 = alloca i32
%"alloca point" = bitcast i32 0 to i32

6
test/CodeGen/PowerPC/LargeAbsoluteAddr.ll
View File

@ -1,9 +1,9 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | \
; RUN: grep "stw r4, 32751"
; RUN: grep "stw r3, 32751"
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep "stw r4, 32751"
; RUN: grep "stw r3, 32751"
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin | \
; RUN: grep "std r4, 9024"
; RUN: grep "std r3, 9024"
define void @test() nounwind {
store i32 0, i32* inttoptr (i64 48725999 to i32*)

21
test/CodeGen/PowerPC/varargs.ll
View File

@ -8,15 +8,16 @@ define i8* @test1(i8** %foo) nounwind {
}
; P32: test1:
; P32: lwz r4, 0(r3)
; P32: addi r5, r4, 4
; P32: stw r5, 0(r3)
; P32: lwz r3, 0(r4)
; P32: blr
; P32: lwz r2, 0(r3)
; P32: addi r4, r2, 4
; P32: stw r4, 0(r3)
; P32: lwz r3, 0(r2)
; P32: blr
; P64: test1:
; P64: ld r4, 0(r3)
; P64: addi r5, r4, 8
; P64: std r5, 0(r3)
; P64: ld r3, 0(r4)
; P64: blr
; P64: ld r2, 0(r3)
; P64: addi r4, r2, 8
; P64: std r4, 0(r3)
; P64: ld r3, 0(r2)
; P64: blr