6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-01 15:17:25 +00:00
Code Issues Projects Releases Wiki Activity

Change interface of MachineOperand as follows:

Browse Source 
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos
2003-12-14 13:24:17 +00:00
parent 97323a47d8
commit 4d7af65903
27 changed files with 163 additions and 185 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@@ -250,7 +250,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
// iterate over all MI operands to find defs
for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI) {
if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
if (OpI.isDef()) // create a new LR since def
addInterference(*OpI, &LVSetAI, isCallInst);
// Calculate the spill cost of each live range
@@ -269,8 +269,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
// instr (currently, only calls have this).
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
for (unsigned z=0; z < NumOfImpRefs; z++)
if (MInst->getImplicitOp(z).opIsDefOnly() ||
MInst->getImplicitOp(z).opIsDefAndUse())
if (MInst->getImplicitOp(z).isDef())
addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
} // for all machine instructions in BB
@@ -295,7 +294,7 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
ItE = MInst->end(); It1 != ItE; ++It1) {
const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
MachineInstr::const_val_op_iterator It2 = It1;
for (++It2; It2 != ItE; ++It2) {
@@ -645,8 +644,8 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
"Return value of a ret must be handled elsewhere");
MachineOperand& Op = MInst->getOperand(OpNum);
bool isDef = Op.opIsDefOnly();
bool isDefAndUse = Op.opIsDefAndUse();
bool isDef = Op.isDef();
bool isUse = Op.isUse();
unsigned RegType = MRI.getRegTypeForLR(LR);
int SpillOff = LR->getSpillOffFromFP();
RegClass *RC = LR->getRegClass();
@@ -699,7 +698,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
assert(scratchReg != MRI.getInvalidRegNum());
}
if (!isDef || isDefAndUse) {
if (isUse) {
// for a USE, we have to load the value of LR from stack to a TmpReg
// and use the TmpReg as one operand of instruction
@@ -712,7 +711,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
AdIMid.clear();
}
if (isDef || isDefAndUse) { // if this is a Def
if (isDef) { // if this is a Def
// for a DEF, we have to store the value produced by this instruction
// on the stack position allocated for this LR