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Replace string GNU Triples with llvm::Triple in TargetMachine. NFC.

Browse Source 
Summary:
For the moment, TargetMachine::getTargetTriple() still returns a StringRef.

This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: ted, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10362

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239554 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2015-06-11 19:41:26 +00:00
parent fd83cb21ce
commit 4ddb0ced90
31 changed files with 190 additions and 193 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/Support/TargetRegistry.h
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@@ -1094,7 +1094,7 @@ private:
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) { CodeGenOpt::Level OL) {
return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL); return new TargetMachineImpl(T, Triple(TT), CPU, FS, Options, RM, CM, OL);
} }
}; };

10
include/llvm/Target/TargetMachine.h
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@@ -15,6 +15,7 @@
#define LLVM_TARGET_TARGETMACHINE_H #define LLVM_TARGET_TARGETMACHINE_H
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Triple.h"
#include "llvm/IR/DataLayout.h" #include "llvm/IR/DataLayout.h"
#include "llvm/Pass.h" #include "llvm/Pass.h"
#include "llvm/Support/CodeGen.h" #include "llvm/Support/CodeGen.h"
@@ -68,7 +69,7 @@ class TargetMachine {
void operator=(const TargetMachine &) = delete; void operator=(const TargetMachine &) = delete;
protected: // Can only create subclasses. protected: // Can only create subclasses.
TargetMachine(const Target &T, StringRef DataLayoutString, TargetMachine(const Target &T, StringRef DataLayoutString,
StringRef TargetTriple, StringRef CPU, StringRef FS, const Triple &TargetTriple, StringRef CPU, StringRef FS,
const TargetOptions &Options); const TargetOptions &Options);
/// The Target that this machine was created for. /// The Target that this machine was created for.
@@ -79,7 +80,7 @@ protected: // Can only create subclasses.
/// Triple string, CPU name, and target feature strings the TargetMachine /// Triple string, CPU name, and target feature strings the TargetMachine
/// instance is created with. /// instance is created with.
std::string TargetTriple; Triple TargetTriple;
std::string TargetCPU; std::string TargetCPU;
std::string TargetFS; std::string TargetFS;
@@ -103,7 +104,8 @@ public:
const Target &getTarget() const { return TheTarget; } const Target &getTarget() const { return TheTarget; }
StringRef getTargetTriple() const { return TargetTriple; } // FIXME: Either rename to getTargetName() or make it return a triple.
StringRef getTargetTriple() const { return TargetTriple.str(); }
StringRef getTargetCPU() const { return TargetCPU; } StringRef getTargetCPU() const { return TargetCPU; }
StringRef getTargetFeatureString() const { return TargetFS; } StringRef getTargetFeatureString() const { return TargetFS; }
@@ -238,7 +240,7 @@ public:
class LLVMTargetMachine : public TargetMachine { class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses. protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef DataLayoutString, LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
StringRef TargetTriple, StringRef CPU, StringRef FS, const Triple &TargetTriple, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);

6
lib/CodeGen/LLVMTargetMachine.cpp
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@@ -72,12 +72,12 @@ void LLVMTargetMachine::initAsmInfo() {
LLVMTargetMachine::LLVMTargetMachine(const Target &T, LLVMTargetMachine::LLVMTargetMachine(const Target &T,
StringRef DataLayoutString, StringRef DataLayoutString,
StringRef Triple, StringRef CPU, const Triple &TT, StringRef CPU,
StringRef FS, TargetOptions Options, StringRef FS, TargetOptions Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: TargetMachine(T, DataLayoutString, Triple, CPU, FS, Options) { : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL); CodeGenInfo = T.createMCCodeGenInfo(TT.str(), RM, CM, OL);
} }
TargetIRAnalysis LLVMTargetMachine::getTargetIRAnalysis() { TargetIRAnalysis LLVMTargetMachine::getTargetIRAnalysis() {

24
lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@@ -120,7 +120,7 @@ static std::string computeDataLayout(const Triple &TT, bool LittleEndian) {
/// TargetMachine ctor - Create an AArch64 architecture model. /// TargetMachine ctor - Create an AArch64 architecture model.
/// ///
AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -163,21 +163,19 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
void AArch64leTargetMachine::anchor() { } void AArch64leTargetMachine::anchor() { }
AArch64leTargetMachine:: AArch64leTargetMachine::AArch64leTargetMachine(
AArch64leTargetMachine(const Target &T, StringRef TT, const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
CodeGenOpt::Level OL) : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
void AArch64beTargetMachine::anchor() { } void AArch64beTargetMachine::anchor() { }
AArch64beTargetMachine:: AArch64beTargetMachine::AArch64beTargetMachine(
AArch64beTargetMachine(const Target &T, StringRef TT, const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
CodeGenOpt::Level OL) : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
: AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
namespace { namespace {
/// AArch64 Code Generator Pass Configuration Options. /// AArch64 Code Generator Pass Configuration Options.

6
lib/Target/AArch64/AArch64TargetMachine.h
View File

@@ -27,7 +27,7 @@ protected:
mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap; mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
public: public:
AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool IsLittleEndian); CodeGenOpt::Level OL, bool IsLittleEndian);
@@ -54,7 +54,7 @@ private:
class AArch64leTargetMachine : public AArch64TargetMachine { class AArch64leTargetMachine : public AArch64TargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU, AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
@@ -65,7 +65,7 @@ public:
class AArch64beTargetMachine : public AArch64TargetMachine { class AArch64beTargetMachine : public AArch64TargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU, AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);

29
lib/Target/ARM/ARMTargetMachine.cpp
View File

@@ -170,17 +170,16 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
/// TargetMachine ctor - Create an ARM architecture model. /// TargetMachine ctor - Create an ARM architecture model.
/// ///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
computeDataLayout(Triple(TT), CPU, Options, isLittle), CPU, FS, Options, RM, CM, OL),
TT, CPU, FS, Options, RM, CM, OL), TargetABI(computeTargetABI(TT, CPU, Options)),
TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) { Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
// Default to triple-appropriate float ABI // Default to triple-appropriate float ABI
if (Options.FloatABIType == FloatABI::Default) if (Options.FloatABIType == FloatABI::Default)
@@ -235,8 +234,9 @@ TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
void ARMTargetMachine::anchor() { } void ARMTargetMachine::anchor() { }
ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, ARMTargetMachine::ARMTargetMachine(const Target &T, const Triple &TT,
StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
@@ -248,7 +248,7 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
void ARMLETargetMachine::anchor() { } void ARMLETargetMachine::anchor() { }
ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT, ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -257,7 +257,7 @@ ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
void ARMBETargetMachine::anchor() { } void ARMBETargetMachine::anchor() { }
ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT, ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -266,19 +266,18 @@ ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
void ThumbTargetMachine::anchor() { } void ThumbTargetMachine::anchor() { }
ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
isLittle) {
initAsmInfo(); initAsmInfo();
} }
void ThumbLETargetMachine::anchor() { } void ThumbLETargetMachine::anchor() { }
ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT, ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -287,7 +286,7 @@ ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
void ThumbBETargetMachine::anchor() { } void ThumbBETargetMachine::anchor() { }
ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT, ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,

34
lib/Target/ARM/ARMTargetMachine.h
View File

@@ -36,12 +36,10 @@ protected:
mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap; mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
public: public:
ARMBaseTargetMachine(const Target &T, StringRef TT, ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, StringRef FS, const TargetOptions &Options,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, CodeGenOpt::Level OL, bool isLittle);
bool isLittle);
~ARMBaseTargetMachine() override; ~ARMBaseTargetMachine() override;
const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
@@ -64,8 +62,8 @@ public:
class ARMTargetMachine : public ARMBaseTargetMachine { class ARMTargetMachine : public ARMBaseTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
}; };
@@ -74,8 +72,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
class ARMLETargetMachine : public ARMTargetMachine { class ARMLETargetMachine : public ARMTargetMachine {
void anchor() override; void anchor() override;
public: public:
ARMLETargetMachine(const Target &T, StringRef TT, ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
}; };
@@ -85,9 +83,10 @@ public:
class ARMBETargetMachine : public ARMTargetMachine { class ARMBETargetMachine : public ARMTargetMachine {
void anchor() override; void anchor() override;
public: public:
ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options,
CodeModel::Model CM, CodeGenOpt::Level OL); Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
}; };
/// ThumbTargetMachine - Thumb target machine. /// ThumbTargetMachine - Thumb target machine.
@@ -97,9 +96,10 @@ public:
class ThumbTargetMachine : public ARMBaseTargetMachine { class ThumbTargetMachine : public ARMBaseTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options,
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
bool isLittle);
}; };
/// ThumbLETargetMachine - Thumb little endian target machine. /// ThumbLETargetMachine - Thumb little endian target machine.
@@ -107,7 +107,7 @@ public:
class ThumbLETargetMachine : public ThumbTargetMachine { class ThumbLETargetMachine : public ThumbTargetMachine {
void anchor() override; void anchor() override;
public: public:
ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU, ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
@@ -118,7 +118,7 @@ public:
class ThumbBETargetMachine : public ThumbTargetMachine { class ThumbBETargetMachine : public ThumbTargetMachine {
void anchor() override; void anchor() override;
public: public:
ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);

9
lib/Target/BPF/BPFTargetMachine.cpp
View File

@@ -29,15 +29,16 @@ extern "C" void LLVMInitializeBPFTarget() {
} }
// DataLayout: little or big endian // DataLayout: little or big endian
static std::string computeDataLayout(StringRef TT) { static std::string computeDataLayout(const Triple &TT) {
if (Triple(TT).getArch() == Triple::bpfeb) if (TT.getArch() == Triple::bpfeb)
return "E-m:e-p:64:64-i64:64-n32:64-S128"; return "E-m:e-p:64:64-i64:64-n32:64-S128";
else else
return "e-m:e-p:64:64-i64:64-n32:64-S128"; return "e-m:e-p:64:64-i64:64-n32:64-S128";
} }
BPFTargetMachine::BPFTargetMachine(const Target &T, StringRef TT, StringRef CPU, BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS,

4
lib/Target/BPF/BPFTargetMachine.h
View File

@@ -23,8 +23,8 @@ class BPFTargetMachine : public LLVMTargetMachine {
BPFSubtarget Subtarget; BPFSubtarget Subtarget;
public: public:
BPFTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; } const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }

4
lib/Target/CppBackend/CPPTargetMachine.h
View File

@@ -23,8 +23,8 @@ namespace llvm {
class formatted_raw_ostream; class formatted_raw_ostream;
struct CPPTargetMachine : public TargetMachine { struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, CPPTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL) CodeModel::Model CM, CodeGenOpt::Level OL)
: TargetMachine(T, "", TT, CPU, FS, Options) {} : TargetMachine(T, "", TT, CPU, FS, Options) {}

4
lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@@ -68,7 +68,7 @@ namespace llvm {
/// Hexagon_TODO: Do I need an aggregate alignment? /// Hexagon_TODO: Do I need an aggregate alignment?
/// ///
HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -76,7 +76,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS, : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<HexagonTargetObjectFile>()), TLOF(make_unique<HexagonTargetObjectFile>()),
Subtarget(Triple(TT), CPU, FS, *this) { Subtarget(TT, CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

2
lib/Target/Hexagon/HexagonTargetMachine.h
View File

@@ -27,7 +27,7 @@ class HexagonTargetMachine : public LLVMTargetMachine {
HexagonSubtarget Subtarget; HexagonSubtarget Subtarget;
public: public:
HexagonTargetMachine(const Target &T, StringRef TT,StringRef CPU, HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);

4
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@@ -25,7 +25,7 @@ extern "C" void LLVMInitializeMSP430Target() {
RegisterTargetMachine<MSP430TargetMachine> X(TheMSP430Target); RegisterTargetMachine<MSP430TargetMachine> X(TheMSP430Target);
} }
MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT, MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -34,7 +34,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT,
Options, RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
// FIXME: Check DataLayout string. // FIXME: Check DataLayout string.
Subtarget(Triple(TT), CPU, FS, *this) { Subtarget(TT, CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

4
lib/Target/MSP430/MSP430TargetMachine.h
View File

@@ -28,8 +28,8 @@ class MSP430TargetMachine : public LLVMTargetMachine {
MSP430Subtarget Subtarget; MSP430Subtarget Subtarget;
public: public:
MSP430TargetMachine(const Target &T, StringRef TT, MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
~MSP430TargetMachine() override; ~MSP430TargetMachine() override;

44
lib/Target/Mips/MipsTargetMachine.cpp
View File

@@ -82,24 +82,20 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
// offset from the stack/frame pointer, using StackGrowsUp enables // offset from the stack/frame pointer, using StackGrowsUp enables
// an easier handling. // an easier handling.
// Using CodeModel::Large enables different CALL behavior. // Using CodeModel::Large enables different CALL behavior.
MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT, MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
computeDataLayout(Triple(TT), CPU, Options, isLittle), CPU, FS, Options, RM, CM, OL),
TT, CPU, FS, Options, RM, CM, OL),
isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()), isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
Subtarget(nullptr), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
DefaultSubtarget(Triple(TT), CPU, FS, isLittle, *this), NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
NoMips16Subtarget(Triple(TT), CPU,
FS.empty() ? "-mips16" : FS.str() + ",-mips16",
isLittle, *this), isLittle, *this),
Mips16Subtarget(Triple(TT), CPU, Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
FS.empty() ? "+mips16" : FS.str() + ",+mips16", isLittle, isLittle, *this) {
*this) {
Subtarget = &DefaultSubtarget; Subtarget = &DefaultSubtarget;
initAsmInfo(); initAsmInfo();
} }
@@ -108,21 +104,21 @@ MipsTargetMachine::~MipsTargetMachine() {}
void MipsebTargetMachine::anchor() { } void MipsebTargetMachine::anchor() { }
MipsebTargetMachine:: MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
void MipselTargetMachine::anchor() { } void MipselTargetMachine::anchor() { }
MipselTargetMachine:: MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
const MipsSubtarget * const MipsSubtarget *
MipsTargetMachine::getSubtargetImpl(const Function &F) const { MipsTargetMachine::getSubtargetImpl(const Function &F) const {

12
lib/Target/Mips/MipsTargetMachine.h
View File

@@ -39,8 +39,8 @@ class MipsTargetMachine : public LLVMTargetMachine {
mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap; mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
public: public:
MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
~MipsTargetMachine() override; ~MipsTargetMachine() override;
@@ -73,8 +73,8 @@ public:
class MipsebTargetMachine : public MipsTargetMachine { class MipsebTargetMachine : public MipsTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
MipsebTargetMachine(const Target &T, StringRef TT, MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
}; };
@@ -84,8 +84,8 @@ public:
class MipselTargetMachine : public MipsTargetMachine { class MipselTargetMachine : public MipsTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
MipselTargetMachine(const Target &T, StringRef TT, MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
}; };

24
lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@@ -83,7 +83,7 @@ static std::string computeDataLayout(bool is64Bit) {
return Ret; return Ret;
} }
NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT, NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -91,8 +91,8 @@ NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, StringRef TT,
: LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM, : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
CM, OL), CM, OL),
is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()), is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
Subtarget(Triple(TT), CPU, FS, *this) { Subtarget(TT, CPU, FS, *this) {
if (Triple(TT).getOS() == Triple::NVCL) if (TT.getOS() == Triple::NVCL)
drvInterface = NVPTX::NVCL; drvInterface = NVPTX::NVCL;
else else
drvInterface = NVPTX::CUDA; drvInterface = NVPTX::CUDA;
@@ -103,18 +103,20 @@ NVPTXTargetMachine::~NVPTXTargetMachine() {}
void NVPTXTargetMachine32::anchor() {} void NVPTXTargetMachine32::anchor() {}
NVPTXTargetMachine32::NVPTXTargetMachine32( NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
const Target &T, StringRef TT, StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, const TargetOptions &Options,
CodeGenOpt::Level OL) Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
void NVPTXTargetMachine64::anchor() {} void NVPTXTargetMachine64::anchor() {}
NVPTXTargetMachine64::NVPTXTargetMachine64( NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
const Target &T, StringRef TT, StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, const TargetOptions &Options,
CodeGenOpt::Level OL) Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
namespace { namespace {

11
lib/Target/NVPTX/NVPTXTargetMachine.h
View File

@@ -34,9 +34,10 @@ class NVPTXTargetMachine : public LLVMTargetMachine {
ManagedStringPool ManagedStrPool; ManagedStringPool ManagedStrPool;
public: public:
NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options,
CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit); Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OP,
bool is64bit);
~NVPTXTargetMachine() override; ~NVPTXTargetMachine() override;
const NVPTXSubtarget *getSubtargetImpl(const Function &) const override { const NVPTXSubtarget *getSubtargetImpl(const Function &) const override {
@@ -67,7 +68,7 @@ public:
class NVPTXTargetMachine32 : public NVPTXTargetMachine { class NVPTXTargetMachine32 : public NVPTXTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
@@ -76,7 +77,7 @@ public:
class NVPTXTargetMachine64 : public NVPTXTargetMachine { class NVPTXTargetMachine64 : public NVPTXTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);

24
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@@ -165,14 +165,16 @@ static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
// with what are (currently) non-function specific overrides as it goes into the // with what are (currently) non-function specific overrides as it goes into the
// LLVMTargetMachine constructor and then using the stored value in the // LLVMTargetMachine constructor and then using the stored value in the
// Subtarget constructor below it. // Subtarget constructor below it.
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU, : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
computeFSAdditions(FS, OL, TT), Options, RM, CM, OL), computeFSAdditions(FS, OL, TT.str()), Options, RM, CM,
OL),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
TargetABI(computeTargetABI(Triple(TT), Options)) { TargetABI(computeTargetABI(TT, Options)) {
initAsmInfo(); initAsmInfo();
} }
@@ -180,23 +182,21 @@ PPCTargetMachine::~PPCTargetMachine() {}
void PPC32TargetMachine::anchor() { } void PPC32TargetMachine::anchor() { }
PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
}
void PPC64TargetMachine::anchor() { } void PPC64TargetMachine::anchor() { }
PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
}
const PPCSubtarget * const PPCSubtarget *
PPCTargetMachine::getSubtargetImpl(const Function &F) const { PPCTargetMachine::getSubtargetImpl(const Function &F) const {

12
lib/Target/PowerPC/PPCTargetMachine.h
View File

@@ -32,8 +32,8 @@ private:
mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap; mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
public: public:
PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
~PPCTargetMachine() override; ~PPCTargetMachine() override;
@@ -60,8 +60,8 @@ public:
class PPC32TargetMachine : public PPCTargetMachine { class PPC32TargetMachine : public PPCTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
PPC32TargetMachine(const Target &T, StringRef TT, PPC32TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
}; };
@@ -71,8 +71,8 @@ public:
class PPC64TargetMachine : public PPCTargetMachine { class PPC64TargetMachine : public PPCTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
PPC64TargetMachine(const Target &T, StringRef TT, PPC64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
}; };

29
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@@ -65,15 +65,15 @@ static std::string computeDataLayout(const Triple &TT) {
return Ret; return Ret;
} }
AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT, AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OptLevel) CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
RM, CM, OptLevel), OptLevel),
TLOF(new TargetLoweringObjectFileELF()), TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this),
Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() { IntrinsicInfo() {
setRequiresStructuredCFG(true); setRequiresStructuredCFG(true);
initAsmInfo(); initAsmInfo();
} }
@@ -86,20 +86,21 @@ AMDGPUTargetMachine::~AMDGPUTargetMachine() {
// R600 Target Machine (R600 -> Cayman) // R600 Target Machine (R600 -> Cayman)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
R600TargetMachine::R600TargetMachine(const Target &T, StringRef TT, StringRef FS, R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, StringRef CPU,
CodeModel::Model CM, CodeGenOpt::Level OL) : TargetOptions Options, Reloc::Model RM,
AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) { } CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GCN Target Machine (SI+) // GCN Target Machine (SI+)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
GCNTargetMachine::GCNTargetMachine(const Target &T, StringRef TT, StringRef FS, GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, StringRef CPU,
CodeModel::Model CM, CodeGenOpt::Level OL) : TargetOptions Options, Reloc::Model RM,
AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) { } CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AMDGPU Pass Setup // AMDGPU Pass Setup

10
lib/Target/R600/AMDGPUTargetMachine.h
View File

@@ -37,7 +37,7 @@ protected:
AMDGPUIntrinsicInfo IntrinsicInfo; AMDGPUIntrinsicInfo IntrinsicInfo;
public: public:
AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS, AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef FS,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine(); ~AMDGPUTargetMachine();
@@ -63,7 +63,7 @@ public:
class R600TargetMachine : public AMDGPUTargetMachine { class R600TargetMachine : public AMDGPUTargetMachine {
public: public:
R600TargetMachine(const Target &T, StringRef TT, StringRef FS, R600TargetMachine(const Target &T, const Triple &TT, StringRef FS,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
@@ -77,9 +77,9 @@ public:
class GCNTargetMachine : public AMDGPUTargetMachine { class GCNTargetMachine : public AMDGPUTargetMachine {
public: public:
GCNTargetMachine(const Target &T, StringRef TT, StringRef FS, GCNTargetMachine(const Target &T, const Triple &TT, StringRef FS,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef CPU, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
}; };

23
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@@ -54,15 +54,15 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) {
/// SparcTargetMachine ctor - Create an ILP32 architecture model /// SparcTargetMachine ctor - Create an ILP32 architecture model
/// ///
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit) CodeGenOpt::Level OL, bool is64bit)
: LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
Options, RM, CM, OL), RM, CM, OL),
TLOF(make_unique<SparcELFTargetObjectFile>()), TLOF(make_unique<SparcELFTargetObjectFile>()),
Subtarget(Triple(TT), CPU, FS, *this, is64bit) { Subtarget(TT, CPU, FS, *this, is64bit) {
initAsmInfo(); initAsmInfo();
} }
@@ -106,19 +106,16 @@ void SparcPassConfig::addPreEmitPass(){
void SparcV8TargetMachine::anchor() { } void SparcV8TargetMachine::anchor() { }
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
StringRef TT, StringRef CPU, StringRef CPU, StringRef FS,
StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, Reloc::Model RM, CodeModel::Model CM,
CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
}
void SparcV9TargetMachine::anchor() { } void SparcV9TargetMachine::anchor() { }
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT, SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -127,7 +124,7 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT,
void SparcelTargetMachine::anchor() {} void SparcelTargetMachine::anchor() {}
SparcelTargetMachine::SparcelTargetMachine(const Target &T, StringRef TT, SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,

17
lib/Target/Sparc/SparcTargetMachine.h
View File

@@ -24,10 +24,10 @@ class SparcTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF; std::unique_ptr<TargetLoweringObjectFile> TLOF;
SparcSubtarget Subtarget; SparcSubtarget Subtarget;
public: public:
SparcTargetMachine(const Target &T, StringRef TT, SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
CodeGenOpt::Level OL, bool is64bit); bool is64bit);
~SparcTargetMachine() override; ~SparcTargetMachine() override;
const SparcSubtarget *getSubtargetImpl(const Function &) const override { const SparcSubtarget *getSubtargetImpl(const Function &) const override {
@@ -46,9 +46,8 @@ public:
class SparcV8TargetMachine : public SparcTargetMachine { class SparcV8TargetMachine : public SparcTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
SparcV8TargetMachine(const Target &T, StringRef TT, SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, StringRef FS, const TargetOptions &Options,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
}; };
@@ -58,7 +57,7 @@ public:
class SparcV9TargetMachine : public SparcTargetMachine { class SparcV9TargetMachine : public SparcTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
@@ -68,7 +67,7 @@ class SparcelTargetMachine : public SparcTargetMachine {
virtual void anchor(); virtual void anchor();
public: public:
SparcelTargetMachine(const Target &T, StringRef TT, StringRef CPU, SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);

8
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@@ -78,15 +78,15 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
return Ret; return Ret;
} }
SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT, SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(Triple(TT), CPU, FS), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
Options, RM, CM, OL), RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(Triple(TT), CPU, FS, *this) { Subtarget(TT, CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

2
lib/Target/SystemZ/SystemZTargetMachine.h
View File

@@ -27,7 +27,7 @@ class SystemZTargetMachine : public LLVMTargetMachine {
SystemZSubtarget Subtarget; SystemZSubtarget Subtarget;
public: public:
SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);

2
lib/Target/TargetMachine.cpp
View File

@@ -38,7 +38,7 @@ using namespace llvm;
// //
TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString, TargetMachine::TargetMachine(const Target &T, StringRef DataLayoutString,
StringRef TT, StringRef CPU, StringRef FS, const Triple &TT, StringRef CPU, StringRef FS,
const TargetOptions &Options) const TargetOptions &Options)
: TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU), : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU),
TargetFS(FS), CodeGenInfo(nullptr), AsmInfo(nullptr), MRI(nullptr), TargetFS(FS), CodeGenInfo(nullptr), AsmInfo(nullptr), MRI(nullptr),

11
lib/Target/X86/X86TargetMachine.cpp
View File

@@ -94,14 +94,15 @@ static std::string computeDataLayout(const Triple &TT) {
/// X86TargetMachine ctor - Create an X86 target. /// X86TargetMachine ctor - Create an X86 target.
/// ///
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
StringRef FS, const TargetOptions &Options, StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options, : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
RM, CM, OL), OL),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(Triple(TT), CPU, FS, *this, Options.StackAlignmentOverride) { Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
// Windows stack unwinder gets confused when execution flow "falls through" // Windows stack unwinder gets confused when execution flow "falls through"
// after a call to 'noreturn' function. // after a call to 'noreturn' function.
// To prevent that, we emit a trap for 'unreachable' IR instructions. // To prevent that, we emit a trap for 'unreachable' IR instructions.

4
lib/Target/X86/X86TargetMachine.h
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@@ -29,8 +29,8 @@ class X86TargetMachine final : public LLVMTargetMachine {
mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap; mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;
public: public:
X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
const TargetOptions &Options, Reloc::Model RM, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
~X86TargetMachine() override; ~X86TargetMachine() override;
const X86Subtarget *getSubtargetImpl(const Function &F) const override; const X86Subtarget *getSubtargetImpl(const Function &F) const override;

4
lib/Target/XCore/XCoreTargetMachine.cpp
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@@ -22,7 +22,7 @@ using namespace llvm;
/// XCoreTargetMachine ctor - Create an ILP32 architecture model /// XCoreTargetMachine ctor - Create an ILP32 architecture model
/// ///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
@@ -31,7 +31,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
TT, CPU, FS, Options, RM, CM, OL), TT, CPU, FS, Options, RM, CM, OL),
TLOF(make_unique<XCoreTargetObjectFile>()), TLOF(make_unique<XCoreTargetObjectFile>()),
Subtarget(Triple(TT), CPU, FS, *this) { Subtarget(TT, CPU, FS, *this) {
initAsmInfo(); initAsmInfo();
} }

4
lib/Target/XCore/XCoreTargetMachine.h
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@@ -23,8 +23,8 @@ class XCoreTargetMachine : public LLVMTargetMachine {
std::unique_ptr<TargetLoweringObjectFile> TLOF; std::unique_ptr<TargetLoweringObjectFile> TLOF;
XCoreSubtarget Subtarget; XCoreSubtarget Subtarget;
public: public:
XCoreTargetMachine(const Target &T, StringRef TT, XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
~XCoreTargetMachine() override; ~XCoreTargetMachine() override;