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Silence sign-compare warning and reduce nesting.

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No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195932 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-11-28 19:58:56 +00:00
parent e195f6c29f
commit 4e7a22f970
1 changed files with 7 additions and 7 deletions
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14
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -4239,13 +4239,13 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
DAG.getConstant(Lane + ExtLane, MVT::i64));
}
// Test if V1 is a CONCAT_VECTORS.
if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
if (V1.getOperand(1).getOpcode() == ISD::UNDEF) {
assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements())
&& "Invalid vector lane access");
return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0),
DAG.getConstant(Lane, MVT::i64));
}
if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
V1.getOperand(1).getOpcode() == ISD::UNDEF) {
SDValue Op0 = V1.getOperand(0);
assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() &&
"Invalid vector lane access");
return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0,
DAG.getConstant(Lane, MVT::i64));
}
return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,