From 4e7a22f97069aaa55a6a46a79d83ac96a6fa8813 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Thu, 28 Nov 2013 19:58:56 +0000 Subject: [PATCH] Silence sign-compare warning and reduce nesting. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195932 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index 15232523fe4..6ea4b483eb4 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4239,13 +4239,13 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, DAG.getConstant(Lane + ExtLane, MVT::i64)); } // Test if V1 is a CONCAT_VECTORS. - if (V1.getOpcode() == ISD::CONCAT_VECTORS) { - if (V1.getOperand(1).getOpcode() == ISD::UNDEF) { - assert((Lane < V1.getOperand(0).getValueType().getVectorNumElements()) - && "Invalid vector lane access"); - return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), - DAG.getConstant(Lane, MVT::i64)); - } + if (V1.getOpcode() == ISD::CONCAT_VECTORS && + V1.getOperand(1).getOpcode() == ISD::UNDEF) { + SDValue Op0 = V1.getOperand(0); + assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() && + "Invalid vector lane access"); + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0, + DAG.getConstant(Lane, MVT::i64)); } return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,