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https://github.com/c64scene-ar/llvm-6502.git
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ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -4213,6 +4213,16 @@ def memb_opt : Operand<i32> {
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let DecoderMethod = "DecodeMemBarrierOption";
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let DecoderMethod = "DecodeMemBarrierOption";
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}
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}
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def InstSyncBarrierOptOperand : AsmOperandClass {
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let Name = "InstSyncBarrierOpt";
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let ParserMethod = "parseInstSyncBarrierOptOperand";
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}
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def instsyncb_opt : Operand<i32> {
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let PrintMethod = "printInstSyncBOption";
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let ParserMatchClass = InstSyncBarrierOptOperand;
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let DecoderMethod = "DecodeInstSyncBarrierOption";
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}
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// memory barriers protect the atomic sequences
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// memory barriers protect the atomic sequences
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let hasSideEffects = 1 in {
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let hasSideEffects = 1 in {
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def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
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def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
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@ -4233,7 +4243,7 @@ def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
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}
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}
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// ISB has only full system option
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// ISB has only full system option
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def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
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def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
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"isb", "\t$opt", []>,
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"isb", "\t$opt", []>,
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Requires<[IsARM, HasDB]> {
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Requires<[IsARM, HasDB]> {
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bits<4> opt;
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bits<4> opt;
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@ -3109,7 +3109,7 @@ def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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let Inst{3-0} = opt;
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let Inst{3-0} = opt;
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}
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}
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def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
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def t2ISB : AInoP<(outs), (ins instsyncb_opt:$opt), ThumbFrm, NoItinerary,
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"isb", "\t$opt",
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"isb", "\t$opt",
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[]>, Requires<[IsThumb, HasDB]> {
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[]>, Requires<[IsThumb, HasDB]> {
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bits<4> opt;
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bits<4> opt;
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@ -183,6 +183,8 @@ class ARMAsmParser : public MCTargetAsmParser {
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SmallVectorImpl<MCParsedAsmOperand*>&);
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy parseMemBarrierOptOperand(
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OperandMatchResultTy parseMemBarrierOptOperand(
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SmallVectorImpl<MCParsedAsmOperand*>&);
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy parseInstSyncBarrierOptOperand(
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy parseProcIFlagsOperand(
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OperandMatchResultTy parseProcIFlagsOperand(
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SmallVectorImpl<MCParsedAsmOperand*>&);
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SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy parseMSRMaskOperand(
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OperandMatchResultTy parseMSRMaskOperand(
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@ -315,6 +317,7 @@ class ARMOperand : public MCParsedAsmOperand {
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k_CoprocOption,
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k_CoprocOption,
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k_Immediate,
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k_Immediate,
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k_MemBarrierOpt,
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k_MemBarrierOpt,
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k_InstSyncBarrierOpt,
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k_Memory,
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k_Memory,
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k_PostIndexRegister,
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k_PostIndexRegister,
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k_MSRMask,
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k_MSRMask,
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@ -358,6 +361,10 @@ class ARMOperand : public MCParsedAsmOperand {
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ARM_MB::MemBOpt Val;
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ARM_MB::MemBOpt Val;
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};
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};
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struct ISBOptOp {
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ARM_ISB::InstSyncBOpt Val;
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};
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struct IFlagsOp {
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struct IFlagsOp {
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ARM_PROC::IFlags Val;
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ARM_PROC::IFlags Val;
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};
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};
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@ -444,6 +451,7 @@ class ARMOperand : public MCParsedAsmOperand {
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struct CopOp Cop;
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struct CopOp Cop;
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struct CoprocOptionOp CoprocOption;
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struct CoprocOptionOp CoprocOption;
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struct MBOptOp MBOpt;
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struct MBOptOp MBOpt;
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struct ISBOptOp ISBOpt;
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struct ITMaskOp ITMask;
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struct ITMaskOp ITMask;
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struct IFlagsOp IFlags;
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struct IFlagsOp IFlags;
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struct MMaskOp MMask;
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struct MMaskOp MMask;
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@ -504,6 +512,8 @@ public:
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case k_MemBarrierOpt:
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case k_MemBarrierOpt:
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MBOpt = o.MBOpt;
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MBOpt = o.MBOpt;
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break;
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break;
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case k_InstSyncBarrierOpt:
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ISBOpt = o.ISBOpt;
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case k_Memory:
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case k_Memory:
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Memory = o.Memory;
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Memory = o.Memory;
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break;
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break;
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@ -586,6 +596,11 @@ public:
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return MBOpt.Val;
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return MBOpt.Val;
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}
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}
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ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
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assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
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return ISBOpt.Val;
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}
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ARM_PROC::IFlags getProcIFlags() const {
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ARM_PROC::IFlags getProcIFlags() const {
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assert(Kind == k_ProcIFlags && "Invalid access!");
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assert(Kind == k_ProcIFlags && "Invalid access!");
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return IFlags.Val;
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return IFlags.Val;
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@ -925,6 +940,7 @@ public:
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bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
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bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
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bool isToken() const { return Kind == k_Token; }
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bool isToken() const { return Kind == k_Token; }
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bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
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bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
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bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
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bool isMem() const { return Kind == k_Memory; }
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bool isMem() const { return Kind == k_Memory; }
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bool isShifterImm() const { return Kind == k_ShifterImmediate; }
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bool isShifterImm() const { return Kind == k_ShifterImmediate; }
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bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
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bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
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@ -1702,6 +1718,11 @@ public:
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Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
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Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
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}
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}
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void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
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}
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void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
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void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
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Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
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@ -2367,6 +2388,15 @@ public:
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return Op;
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return Op;
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}
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}
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static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
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SMLoc S) {
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ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
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Op->ISBOpt.Val = Opt;
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
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static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
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ARMOperand *Op = new ARMOperand(k_ProcIFlags);
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ARMOperand *Op = new ARMOperand(k_ProcIFlags);
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Op->IFlags.Val = IFlags;
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Op->IFlags.Val = IFlags;
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@ -2421,6 +2451,9 @@ void ARMOperand::print(raw_ostream &OS) const {
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case k_MemBarrierOpt:
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case k_MemBarrierOpt:
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OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
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OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
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break;
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break;
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case k_InstSyncBarrierOpt:
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OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
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break;
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case k_Memory:
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case k_Memory:
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OS << "<memory "
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OS << "<memory "
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<< " base:" << Memory.BaseRegNum;
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<< " base:" << Memory.BaseRegNum;
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@ -3405,6 +3438,57 @@ parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return MatchOperand_Success;
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return MatchOperand_Success;
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}
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}
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/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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const AsmToken &Tok = Parser.getTok();
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unsigned Opt;
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if (Tok.is(AsmToken::Identifier)) {
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StringRef OptStr = Tok.getString();
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if (OptStr.lower() == "sy")
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Opt = ARM_ISB::SY;
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else
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return MatchOperand_NoMatch;
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Parser.Lex(); // Eat identifier token.
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} else if (Tok.is(AsmToken::Hash) ||
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Tok.is(AsmToken::Dollar) ||
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Tok.is(AsmToken::Integer)) {
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if (Parser.getTok().isNot(AsmToken::Integer))
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Parser.Lex(); // Eat the '#'.
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SMLoc Loc = Parser.getTok().getLoc();
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const MCExpr *ISBarrierID;
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if (getParser().parseExpression(ISBarrierID)) {
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Error(Loc, "illegal expression");
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return MatchOperand_ParseFail;
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}
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
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if (!CE) {
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Error(Loc, "constant expression expected");
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return MatchOperand_ParseFail;
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}
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int Val = CE->getValue();
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if (Val & ~0xf) {
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Error(Loc, "immediate value out of range");
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return MatchOperand_ParseFail;
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}
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Opt = ARM_ISB::RESERVED_0 + Val;
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} else
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return MatchOperand_ParseFail;
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Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
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(ARM_ISB::InstSyncBOpt)Opt, S));
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return MatchOperand_Success;
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}
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/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
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/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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@ -279,6 +279,8 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
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static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
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static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
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static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
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@ -3553,6 +3555,15 @@ static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
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return MCDisassembler::Success;
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return MCDisassembler::Success;
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}
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}
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static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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if (Val & ~0xf)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateImm(Val));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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uint64_t Address, const void *Decoder) {
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if (!Val) return MCDisassembler::Fail;
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if (!Val) return MCDisassembler::Fail;
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@ -674,6 +674,12 @@ void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
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O << ARM_MB::MemBOptToString(val);
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O << ARM_MB::MemBOptToString(val);
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}
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}
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void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned val = MI->getOperand(OpNum).getImm();
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O << ARM_ISB::InstSyncBOptToString(val);
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}
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void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
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void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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raw_ostream &O) {
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unsigned ShiftOp = MI->getOperand(OpNum).getImm();
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unsigned ShiftOp = MI->getOperand(OpNum).getImm();
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@ -71,6 +71,7 @@ public:
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void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
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void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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raw_ostream &O);
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void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printInstSyncBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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@ -161,6 +161,49 @@ namespace ARM_MB {
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}
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}
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} // namespace ARM_MB
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} // namespace ARM_MB
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namespace ARM_ISB {
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enum InstSyncBOpt {
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RESERVED_0 = 0,
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RESERVED_1 = 1,
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RESERVED_2 = 2,
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RESERVED_3 = 3,
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RESERVED_4 = 4,
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RESERVED_5 = 5,
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RESERVED_6 = 6,
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RESERVED_7 = 7,
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RESERVED_8 = 8,
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RESERVED_9 = 9,
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RESERVED_10 = 10,
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RESERVED_11 = 11,
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RESERVED_12 = 12,
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RESERVED_13 = 13,
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RESERVED_14 = 14,
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SY = 15
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};
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inline static const char *InstSyncBOptToString(unsigned val) {
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switch (val) {
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default: llvm_unreachable("Unkown memory operation");
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case RESERVED_0: return "#0x0";
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case RESERVED_1: return "#0x1";
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case RESERVED_2: return "#0x2";
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case RESERVED_3: return "#0x3";
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case RESERVED_4: return "#0x4";
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case RESERVED_5: return "#0x5";
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case RESERVED_6: return "#0x6";
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case RESERVED_7: return "#0x7";
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case RESERVED_8: return "#0x8";
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case RESERVED_9: return "#0x9";
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case RESERVED_10: return "#0xa";
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case RESERVED_11: return "#0xb";
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case RESERVED_12: return "#0xc";
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case RESERVED_13: return "#0xd";
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case RESERVED_14: return "#0xe";
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case SY: return "sy";
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}
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}
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} // namespace ARM_ISB
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/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
|
/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
|
||||||
///
|
///
|
||||||
static inline bool isARMLowRegister(unsigned Reg) {
|
static inline bool isARMLowRegister(unsigned Reg) {
|
||||||
|
@ -778,9 +778,13 @@ Lforward:
|
|||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
isb sy
|
isb sy
|
||||||
isb
|
isb
|
||||||
|
isb #15
|
||||||
|
isb #1
|
||||||
|
|
||||||
@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
|
@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
|
||||||
@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
|
@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
|
||||||
|
@ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5]
|
||||||
|
@ CHECK: isb #0x1 @ encoding: [0x61,0xf0,0x7f,0xf5]
|
||||||
|
|
||||||
|
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
|
@ -571,9 +571,13 @@ _func:
|
|||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
isb sy
|
isb sy
|
||||||
isb
|
isb
|
||||||
|
isb #15
|
||||||
|
isb #1
|
||||||
|
|
||||||
@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
|
@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
|
||||||
@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
|
@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
|
||||||
|
@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
|
||||||
|
@ CHECK: isb #0x1 @ encoding: [0xbf,0xf3,0x61,0x8f]
|
||||||
|
|
||||||
|
|
||||||
@------------------------------------------------------------------------------
|
@------------------------------------------------------------------------------
|
||||||
|
@ -371,3 +371,8 @@
|
|||||||
@ CHECK-ERRORS: error: invalid operand for instruction
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
||||||
@ CHECK-ERRORS: msr foo, #0
|
@ CHECK-ERRORS: msr foo, #0
|
||||||
@ CHECK-ERRORS: ^
|
@ CHECK-ERRORS: ^
|
||||||
|
|
||||||
|
isb #-1
|
||||||
|
isb #16
|
||||||
|
@ CHECK-ERRORS: error: immediate value out of range
|
||||||
|
@ CHECK-ERRORS: error: immediate value out of range
|
||||||
|
@ -42,3 +42,8 @@
|
|||||||
@ CHECK-ERRORS: error: invalid operand for instruction
|
@ CHECK-ERRORS: error: invalid operand for instruction
|
||||||
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
|
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
|
||||||
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
|
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
|
||||||
|
|
||||||
|
isb #-1
|
||||||
|
isb #16
|
||||||
|
@ CHECK-ERRORS: error: immediate value out of range
|
||||||
|
@ CHECK-ERRORS: error: immediate value out of range
|
||||||
|
@ -613,8 +613,10 @@
|
|||||||
# ISB
|
# ISB
|
||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
# CHECK: isb sy
|
# CHECK: isb sy
|
||||||
|
# CHECK: isb #0xa
|
||||||
|
|
||||||
0x6f 0xf0 0x7f 0xf5
|
0x6f 0xf0 0x7f 0xf5
|
||||||
|
0x6a 0xf0 0x7f 0xf5
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
@ -447,8 +447,10 @@
|
|||||||
# ISB
|
# ISB
|
||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
#CHECK: isb sy
|
#CHECK: isb sy
|
||||||
|
#CHECK: isb #0xa
|
||||||
|
|
||||||
0xbf 0xf3 0x6f 0x8f
|
0xbf 0xf3 0x6f 0x8f
|
||||||
|
0xbf 0xf3 0x6a 0x8f
|
||||||
|
|
||||||
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
||||||
# IT
|
# IT
|
||||||
|
Reference in New Issue
Block a user