6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-12 18:33:22 +00:00
Code Issues Projects Releases Wiki Activity

This isn't safe when there are uses of load's chain result.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40617 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-07-31 06:21:44 +00:00
parent 6240ab5022
commit 4ebcc8c2f8
1 changed files with 4 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/X86/X86ISelLowering.cpp
View File

@ -3010,18 +3010,11 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
// Use two pinsrw instructions to insert a 32 bit value. // Use two pinsrw instructions to insert a 32 bit value.
Idx <<= 1; Idx <<= 1;
if (MVT::isFloatingPoint(N1.getValueType())) { if (MVT::isFloatingPoint(N1.getValueType())) {
if (ISD::isNON_EXTLoad(N1.Val)) {
// Just load directly from f32mem to GR32.
LoadSDNode *LD = cast<LoadSDNode>(N1);
N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset());
} else {
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1); N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1); N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1, N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
DAG.getConstant(0, getPointerTy())); DAG.getConstant(0, getPointerTy()));
} }
}
N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0); N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1, N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
DAG.getConstant(Idx, getPointerTy())); DAG.getConstant(Idx, getPointerTy()));