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Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99501 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-03-25 07:16:57 +00:00
parent 5a6e97a7e4
commit 4ec9bd9a6f
1 changed files with 8 additions and 0 deletions
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8
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
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@ -528,8 +528,16 @@ EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
if (!MI)
continue;
MachineBasicBlock *MIBB = MI->getParent();
#ifndef NDEBUG
unsigned LastDIOrder = 0;
#endif
for (; DI != DE &&
(*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
#ifndef NDEBUG
assert((*DI)->getOrder() >= LastDIOrder &&
"SDDbgValue nodes must be in source order!");
LastDIOrder = (*DI)->getOrder();
#endif
if ((*DI)->isInvalidated())
continue;
MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);