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Fix CodeGen for unaligned loads with address spaces

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193721 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2013-10-30 23:30:05 +00:00
parent 9effcbb879
commit 4f17f88071
2 changed files with 24 additions and 2 deletions
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7
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -311,6 +311,8 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
SDValue Val = ST->getValue();
EVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
unsigned AS = ST->getAddressSpace();
SDLoc dl(ST);
if (ST->getMemoryVT().isFloatingPoint() ||
ST->getMemoryVT().isVector()) {
@ -343,7 +345,7 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
SDValue Store = DAG.getTruncStore(Chain, dl,
Val, StackPtr, MachinePointerInfo(),
StoredVT, false, false, 0);
SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
SmallVector<SDValue, 8> Stores;
unsigned Offset = 0;
@ -409,8 +411,9 @@ static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
ST->getPointerInfo(), NewStoredVT,
ST->isVolatile(), ST->isNonTemporal(), Alignment);
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getConstant(IncrementSize, TLI.getPointerTy()));
DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
Alignment = MinAlign(Alignment, IncrementSize);
Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),

19
test/CodeGen/R600/unaligned-load-store.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @unaligned_load_store_i32:
; SI: V_ADD_I32_e64 [[REG:VGPR[0-9]+]]
; DS_READ_U8 {{VGPR[0-9]+}}, 0, [[REG]]
define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
%v = load i32 addrspace(3)* %p, align 1
store i32 %v, i32 addrspace(3)* %r, align 1
ret void
}
; SI-LABEL: @unaligned_load_store_v4i32:
; SI: V_ADD_I32_e64 [[REG:VGPR[0-9]+]]
; DS_READ_U8 {{VGPR[0-9]+}}, 0, [[REG]]
define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
%v = load <4 x i32> addrspace(3)* %p, align 1
store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1
ret void
}