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Flag unallocatable register classes instead of giving them empty

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allocation orders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-06-02 23:07:24 +00:00
parent f462e3fac7
commit 4f3fb6d08b
3 changed files with 8 additions and 39 deletions
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4
lib/Target/ARM/ARMRegisterInfo.td
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@ -540,4 +540,6 @@ def QQQQPR : RegisterClass<"ARM", [v8i64],
} }
// Condition code registers. // Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]> {
let isAllocatable = 0;
}

22
lib/Target/X86/X86RegisterInfo.td
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@ -681,15 +681,7 @@ def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
// for transforming FPn allocations to STn registers) // for transforming FPn allocations to STn registers)
def RST : RegisterClass<"X86", [f80, f64, f32], 32, def RST : RegisterClass<"X86", [f80, f64, f32], 32,
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
let MethodProtos = [{ let isAllocatable = 0;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
RSTClass::iterator
RSTClass::allocation_order_end(const MachineFunction &MF) const {
return begin();
}
}];
} }
// Generic vector registers: VR64 and VR128. // Generic vector registers: VR64 and VR128.
@ -742,15 +734,5 @@ def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
// Status flags registers. // Status flags registers.
def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> { def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
let CopyCost = -1; // Don't allow copying of status registers. let CopyCost = -1; // Don't allow copying of status registers.
let isAllocatable = 0;
// EFLAGS is not allocatable.
let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
CCRClass::iterator
CCRClass::allocation_order_end(const MachineFunction &MF) const {
return allocation_order_begin(MF);
}
}];
} }

21
lib/Target/XCore/XCoreRegisterInfo.td
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@ -70,22 +70,7 @@ def GRRegs : RegisterClass<"XCore", [i32], 32,
}]; }];
} }
def RRegs : RegisterClass<"XCore", [i32], 32, // Reserved
// Reserved def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> {
[CP, DP, SP, LR]> { let isAllocatable = 0;
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
RRegsClass::iterator
RRegsClass::allocation_order_begin(const MachineFunction &MF) const {
return begin();
}
RRegsClass::iterator
RRegsClass::allocation_order_end(const MachineFunction &MF) const {
// No allocatable registers
return begin();
}
}];
} }