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https://github.com/c64scene-ar/llvm-6502.git
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- Only use pshufd for v4i32 vector shuffles.
- Other shuffle related fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27244 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
f3a627262c
commit
4f5633883b
@ -1583,15 +1583,21 @@ unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
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return Mask;
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}
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/// CommuteVectorShuffleIfNeeded - Swap vector_shuffle operands (as well as
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/// values in ther permute mask if needed. Return an empty SDOperand is it is
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/// already well formed.
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static SDOperand CommuteVectorShuffleIfNeeded(SDOperand V1, SDOperand V2,
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SDOperand Mask, MVT::ValueType VT,
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SelectionDAG &DAG) {
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/// NormalizeVectorShuffle - Swap vector_shuffle operands (as well as
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/// values in ther permute mask if needed. Use V1 as second vector if it is
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/// undef. Return an empty SDOperand is it is already well formed.
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static SDOperand NormalizeVectorShuffle(SDOperand V1, SDOperand V2,
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SDOperand Mask, MVT::ValueType VT,
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SelectionDAG &DAG) {
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unsigned NumElems = Mask.getNumOperands();
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SDOperand Half1 = Mask.getOperand(0);
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SDOperand Half2 = Mask.getOperand(NumElems/2);
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bool V2Undef = false;
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if (V2.getOpcode() == ISD::UNDEF) {
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V2Undef = true;
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V2 = V1;
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}
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if (cast<ConstantSDNode>(Half1)->getValue() >= NumElems &&
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cast<ConstantSDNode>(Half2)->getValue() < NumElems) {
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// Swap the operands and change mask.
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@ -1604,6 +1610,10 @@ static SDOperand CommuteVectorShuffleIfNeeded(SDOperand V1, SDOperand V2,
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DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), MaskVec);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1, Mask);
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}
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if (V2Undef)
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
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return SDOperand();
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}
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@ -2387,8 +2397,26 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType VT = Op.getValueType();
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unsigned NumElems = PermMask.getNumOperands();
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if (NumElems == 2)
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return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
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if (X86::isUNPCKLMask(PermMask.Val) ||
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X86::isUNPCKHMask(PermMask.Val))
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// Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
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return SDOperand();
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// PSHUFD's 2nd vector must be undef.
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if (MVT::isInteger(VT) && X86::isPSHUFDMask(PermMask.Val))
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if (V2.getOpcode() == ISD::UNDEF)
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return SDOperand();
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else
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
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DAG.getNode(ISD::UNDEF, V1.getValueType()),
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PermMask);
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if (NumElems == 2 ||
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X86::isSplatMask(PermMask.Val) ||
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X86::isSHUFPMask(PermMask.Val)) {
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return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
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}
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#if 0
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else if (X86::isSplatMask(PermMask.Val)) {
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// Handle splat cases.
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if (V2.getOpcode() == ISD::UNDEF)
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@ -2400,10 +2428,6 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
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DAG.getNode(ISD::UNDEF, V1.getValueType()),
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PermMask);
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} else if (X86::isUNPCKLMask(PermMask.Val) ||
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X86::isUNPCKHMask(PermMask.Val)) {
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// Leave the VECTOR_SHUFFLE alone. It matches {P}UNPCKL*.
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return SDOperand();
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} else if (X86::isPSHUFDMask(PermMask.Val)) {
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if (V2.getOpcode() == ISD::UNDEF)
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// Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
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@ -2414,7 +2438,8 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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DAG.getNode(ISD::UNDEF, V1.getValueType()),
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PermMask);
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} else if (X86::isSHUFPMask(PermMask.Val))
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return CommuteVectorShuffleIfNeeded(V1, V2, PermMask, VT, DAG);
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return NormalizeVectorShuffle(V1, V2, PermMask, VT, DAG);
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#endif
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assert(0 && "Unexpected VECTOR_SHUFFLE to lower");
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abort();
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@ -79,9 +79,8 @@ def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHMask(N);
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}]>;
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// Only use PSHUF if it is not a splat.
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def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
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return !X86::isSplatMask(N) && X86::isPSHUFDMask(N);
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return X86::isPSHUFDMask(N);
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}], SHUFFLE_get_shuf_imm>;
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def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
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@ -918,86 +917,92 @@ def PSHUFWrm : PSIi8<0x70, MRMSrcMem,
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFDrr : PDIi8<0x70, MRMDestReg,
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(ops VR128:$dst, VR128:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v4i32 (vector_shuffle
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VR128:$src1, (undef),
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PSHUFD_shuffle_mask:$src2)))]>;
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def PSHUFDrm : PDIi8<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v4i32 (vector_shuffle
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(load addr:$src1), (undef),
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PSHUFD_shuffle_mask:$src2)))]>;
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let isTwoAddress = 1 in {
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def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (vector_shuffle
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(v4f32 VR128:$src1), (v4f32 VR128:$src2),
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SHUFP_shuffle_mask:$src3))]>;
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src1, VR128:$src2,
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SHUFP_shuffle_mask:$src3)))]>;
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def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
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"shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (vector_shuffle
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(v4f32 VR128:$src1), (load addr:$src2),
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SHUFP_shuffle_mask:$src3))]>;
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src1, (load addr:$src2),
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SHUFP_shuffle_mask:$src3)))]>;
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def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (vector_shuffle
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(v2f64 VR128:$src1), (v2f64 VR128:$src2),
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SHUFP_shuffle_mask:$src3))]>;
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src1, VR128:$src2,
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SHUFP_shuffle_mask:$src3)))]>;
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def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
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"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst, (vector_shuffle
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(v2f64 VR128:$src1), (load addr:$src2),
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SHUFP_shuffle_mask:$src3))]>;
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src1, (load addr:$src2),
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SHUFP_shuffle_mask:$src3)))]>;
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def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"unpckhps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKH_shuffle_mask)))]>;
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src1, VR128:$src2,
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UNPCKH_shuffle_mask)))]>;
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def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"unpckhps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKH_shuffle_mask)))]>;
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src1, (load addr:$src2),
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UNPCKH_shuffle_mask)))]>;
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def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"unpckhpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKH_shuffle_mask)))]>;
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src1, VR128:$src2,
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UNPCKH_shuffle_mask)))]>;
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def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"unpckhpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKH_shuffle_mask)))]>;
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src1, (load addr:$src2),
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UNPCKH_shuffle_mask)))]>;
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def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"unpcklps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"unpcklps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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[(set VR128:$dst, (v4f32 (vector_shuffle
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VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"unpcklpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src1, VR128:$src2,
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UNPCKL_shuffle_mask)))]>;
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def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"unpcklpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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[(set VR128:$dst, (v2f64 (vector_shuffle
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VR128:$src1, (load addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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}
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//===----------------------------------------------------------------------===//
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@ -1354,11 +1359,3 @@ def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
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(v2f64 (MOVLHPSrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
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def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
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(v2i64 (MOVLHPSrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
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// Shuffle v4f32 / v4i32, undef. These should only match if splat cases do not.
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def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
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(v4f32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
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Requires<[HasSSE2]>;
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def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
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(v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
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Requires<[HasSSE2]>;
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