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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-19 20:34:38 +00:00
add matches for SxADDL and company, as well as simplify the SxADDQ code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21281 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1490,47 +1490,43 @@ unsigned ISel::SelectExpr(SDOperand N) {
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bool isAdd = N.getOperand(0).getOpcode() == ISD::ADD;
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bool isMul = N.getOperand(0).getOpcode() == ISD::MUL;
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//FIXME: first check for Scaled Adds and Subs!
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if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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ConstantSDNode* CSD = NULL;
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if(!isMul && N.getOperand(0).getOperand(0).getOpcode() == ISD::SHL &&
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(0).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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{
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bool use4 = CSD->getValue() == 2;
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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BuildMI(BB, isAdd?(use4?Alpha::S4ADDL:Alpha::S8ADDL):(use4?Alpha::S4SUBL:Alpha::S8SUBL),
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2,Result).addReg(Tmp1).addReg(Tmp2);
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}
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else if(isAdd && N.getOperand(0).getOperand(1).getOpcode() == ISD::SHL &&
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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{
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bool use4 = CSD->getValue() == 2;
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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BuildMI(BB, use4?Alpha::S4ADDL:Alpha::S8ADDL, 2,Result).addReg(Tmp1).addReg(Tmp2);
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}
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else if(N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() <= 255)
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{ //Normal imm add/sub
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Opc = isAdd ? Alpha::ADDLi : (isMul ? Alpha::MULLi : Alpha::SUBLi);
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//if the value was really originally a i32, skip the up conversion
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if (N.getOperand(0).getOperand(0).getOpcode() == ISD::SIGN_EXTEND_INREG &&
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dyn_cast<MVTSDNode>(N.getOperand(0).getOperand(0).Val)
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->getExtraValueType() == MVT::i32)
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
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else
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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}
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else
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{ //Normal add/sub
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Opc = isAdd ? Alpha::ADDL : (isMul ? Alpha::MULLi : Alpha::SUBL);
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//if the value was really originally a i32, skip the up conversion
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if (N.getOperand(0).getOperand(0).getOpcode() == ISD::SIGN_EXTEND_INREG &&
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dyn_cast<MVTSDNode>(N.getOperand(0).getOperand(0).Val)
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->getExtraValueType() == MVT::i32)
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
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else
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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//if the value was really originally a i32, skip the up conversion
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if (N.getOperand(0).getOperand(1).getOpcode() == ISD::SIGN_EXTEND_INREG &&
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dyn_cast<MVTSDNode>(N.getOperand(0).getOperand(1).Val)
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->getExtraValueType() == MVT::i32)
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
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else
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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Opc = isAdd ? Alpha::ADDL : (isMul ? Alpha::MULL : Alpha::SUBL);
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Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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}
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return Result;
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}
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case ISD::SEXTLOAD:
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//SelectionDag isn't deleting the signextend after sextloads
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Reg = Result = SelectExpr(N.getOperand(0));
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return Result;
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default: break; //Fall Though;
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}
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} //Every thing else fall though too, including unhandled opcodes above
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@ -1787,79 +1783,52 @@ unsigned ISel::SelectExpr(SDOperand N) {
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//first check for Scaled Adds and Subs!
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//Valid for add and sub
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ConstantSDNode* CSD = NULL;
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if(N.getOperand(0).getOpcode() == ISD::SHL &&
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N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 2)
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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{
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bool use4 = CSD->getValue() == 2;
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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if (N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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BuildMI(BB, isAdd?Alpha::S4ADDQi:Alpha::S4SUBQi, 2, Result).addReg(Tmp2)
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.addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue());
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if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) && CSD->getValue() <= 255)
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BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
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2, Result).addReg(Tmp2).addImm(CSD->getValue());
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else {
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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}
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else if(N.getOperand(0).getOpcode() == ISD::SHL &&
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N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 3)
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{
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Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
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if (N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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BuildMI(BB, isAdd?Alpha::S8ADDQi:Alpha::S8SUBQi, 2, Result).addReg(Tmp2)
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.addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue());
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else {
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, isAdd?Alpha::S8ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
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2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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}
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//Position prevents subs
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else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &
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N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 2)
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{
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Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
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if (N.getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
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BuildMI(BB, Alpha::S4ADDQi, 2, Result).addReg(Tmp2)
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.addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue());
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else {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::S4ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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}
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else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &&
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N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 3)
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(CSD = dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) &&
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(CSD->getValue() == 2 || CSD->getValue() == 3))
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{
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bool use4 = CSD->getValue() == 2;
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Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
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if (N.getOperand(0).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
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BuildMI(BB, Alpha::S8ADDQi, 2, Result).addReg(Tmp2)
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.addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue());
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if ((CSD = dyn_cast<ConstantSDNode>(N.getOperand(0))) && CSD->getValue() <= 255)
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BuildMI(BB, use4?Alpha::S4ADDQi:Alpha::S8ADDQi, 2, Result).addReg(Tmp2)
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.addImm(CSD->getValue());
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else {
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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BuildMI(BB, use4?Alpha::S4ADDQ:Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
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}
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}
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//small addi
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else if(N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
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else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
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CSD->getValue() <= 255)
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{ //Normal imm add/sub
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Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(CSD->getValue());
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}
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//larger addi
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else if(N.getOperand(1).getOpcode() == ISD::Constant &&
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(cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767 ||
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(long)cast<ConstantSDNode>(N.getOperand(1))->getValue() >= -32767))
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else if((CSD = dyn_cast<ConstantSDNode>(N.getOperand(1))) &&
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CSD->getSignExtended() <= 32767 &&
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CSD->getSignExtended() >= -32767)
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{ //LDA
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = (long)cast<ConstantSDNode>(N.getOperand(1))->getValue();
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Tmp2 = (long)CSD->getSignExtended();
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if (!isAdd)
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Tmp2 = -Tmp2;
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BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp2).addReg(Tmp1);
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@ -2270,3 +2239,4 @@ void ISel::Select(SDOperand N) {
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FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) {
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return new ISel(TM);
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}
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