diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index b2fc53af177..bb1dfd2b36b 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -393,10 +393,23 @@ public:
     abort();
   }
 
+  /// isPredicable - Returns true if the instruction is already predicated.
+  ///
+  virtual bool isPredicated(MachineInstr *MI) const {
+    return false;
+  }
+
   /// PredicateInstruction - Convert the instruction into a predicated
   /// instruction. It returns true if the operation was successful.
   virtual bool PredicateInstruction(MachineInstr *MI,
-                                    std::vector<MachineOperand> &Cond) const;
+                                    std::vector<MachineOperand> &Pred) const;
+
+  /// SubsumesPredicate - Returns true if the first specified predicated
+  /// subsumes the second, e.g. GE subsumes GT.
+  virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1,
+                                 std::vector<MachineOperand> &Pred2) const {
+    return false;
+  }
 
   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
   /// values.