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Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200349 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse
2014-01-28 23:13:18 +00:00
parent 2ddea4b44d
commit 4faa861f19
10 changed files with 555 additions and 315 deletions
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27
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
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@@ -45,17 +45,21 @@ public:
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@@ -71,7 +75,7 @@ void SparcMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
unsigned Bits = getBinaryCodeForInstr(MI, Fixups);
unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
// Output the constant in big endian byte order.
for (unsigned i = 0; i != 4; ++i) {
@@ -85,7 +89,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
unsigned SparcMCCodeEmitter::
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg())
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
@@ -140,10 +145,11 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
unsigned SparcMCCodeEmitter::
getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups);
return getMachineOpValue(MI, MO, Fixups, STI);
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)Sparc::fixup_sparc_call30));
@@ -152,10 +158,11 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
unsigned SparcMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm())
return getMachineOpValue(MI, MO, Fixups);
return getMachineOpValue(MI, MO, Fixups, STI);
Sparc::Fixups fixup = Sparc::fixup_sparc_br22;
if (MI.getOpcode() == SP::BPXCC)