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Sign extending pre/post indexed loads.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-02 23:16:11 +00:00
parent eeb4a84ac8
commit 4fbb9960ad
3 changed files with 42 additions and 3 deletions
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12
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -794,6 +794,7 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
return NULL;
MVT LoadedVT = LD->getMemoryVT();
bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
SDValue Offset;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
@ -804,10 +805,17 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
break;
case MVT::i16:
Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
else
Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
break;
case MVT::i8:
Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
case MVT::i1:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
else
Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
break;
default:
return NULL;

22
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -579,6 +579,28 @@ def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
"ldrh", " $dst, [$base], $offset", "$base = $base_wb",
[]>;
def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre,
"ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
[]>;
def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost,
"ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
[]>;
def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre,
"ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
[]>;
def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, t2am_imm8_offset:$offset),
AddrModeT2_i8, IndexModePost,
"ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
[]>;
// Store
defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;

11
test/CodeGen/Thumb2/thumb2-ldr_pre.ll
View File

@ -1,5 +1,7 @@
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
; RUN: grep {ldr.*\\!} | count 2
; RUN: grep {ldr.*\\!} | count 3
; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | \
; RUN: grep {ldrsb.*\\!} | count 1
define i32* @test1(i32* %X, i32* %dest) {
%Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2]
@ -17,3 +19,10 @@ define i32 @test2(i32 %a, i32 %b) {
ret i32 %tmp5
}
define i8* @test3(i8* %X, i32* %dest) {
%tmp1 = getelementptr i8* %X, i32 4
%tmp2 = load i8* %tmp1
%tmp3 = sext i8 %tmp2 to i32
store i32 %tmp3, i32* %dest
ret i8* %tmp1
}