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Sign extending pre/post indexed loads.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-07-02 23:16:11 +00:00
parent eeb4a84ac8
commit 4fbb9960ad
3 changed files with 42 additions and 3 deletions
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12
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -794,6 +794,7 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
return NULL;
MVT LoadedVT = LD->getMemoryVT();
bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
SDValue Offset;
bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
unsigned Opcode = 0;
@@ -804,10 +805,17 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
break;
case MVT::i16:
Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
else
Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
break;
case MVT::i8:
Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
case MVT::i1:
if (isSExtLd)
Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
else
Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
break;
default:
return NULL;