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Correct the pre-increment load latencies in the PPC A2 itinerary

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Pre-increment loads are microcoded on the A2, and the address increment occurs
only after the load completes. As a result, the latency of the GPR address
update is an additional 2 cycles on top of the load latency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191156 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-09-22 00:08:14 +00:00
parent 20b5879e0e
commit 50019d8f7e
1 changed files with 3 additions and 3 deletions
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6
lib/Target/PowerPC/PPCScheduleA2.td
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@ -70,7 +70,7 @@ def PPCA2Itineraries : ProcessorItineraries<
InstrItinData<LdStLoad , [InstrStage<1, [XU]>],
[6, 1, 1]>,
InstrItinData<LdStLoadUpd , [InstrStage<1, [XU]>],
[6, 2, 1, 1]>,
[6, 8, 1, 1]>,
InstrItinData<LdStLDU , [InstrStage<1, [XU]>],
[6, 1, 1]>,
InstrItinData<LdStStore , [InstrStage<1, [XU]>],
@ -86,11 +86,11 @@ def PPCA2Itineraries : ProcessorItineraries<
InstrItinData<LdStLFD , [InstrStage<1, [XU]>],
[7, 1, 1]>,
InstrItinData<LdStLFDU , [InstrStage<1, [XU]>],
[7, 2, 1, 1]>,
[7, 9, 1, 1]>,
InstrItinData<LdStLHA , [InstrStage<1, [XU]>],
[6, 1, 1]>,
InstrItinData<LdStLHAU , [InstrStage<1, [XU]>],
[6, 2, 1, 1]>,
[6, 8, 1, 1]>,
InstrItinData<LdStLWARX , [InstrStage<1, [XU]>],
[82, 1, 1]>, // L2 latency
InstrItinData<LdStSTD , [InstrStage<1, [XU]>],