6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-10 02:36:06 +00:00
Code Issues Projects Releases Wiki Activity

Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-18 20:07:47 +00:00
parent 27e4840e03
commit 5012f9b825
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -551,11 +551,12 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
const TargetRegisterClass *SRC = const TargetRegisterClass *SRC =
TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
//getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0));
if (!SRC) if (!SRC)
llvm_unreachable("Invalid subregister index in REG_SEQUENCE"); llvm_unreachable("Invalid subregister index in REG_SEQUENCE");
if (SRC != RC) if (SRC != RC) {
MRI->setRegClass(NewVReg, SRC); MRI->setRegClass(NewVReg, SRC);
RC = SRC;
}
} }
AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
IsClone, IsCloned); IsClone, IsCloned);