6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-05 01:31:05 +00:00
Code Issues Projects Releases Wiki Activity

Implement splitting support for store, allowing us to compile:

Browse Source 
%f8 = type <8 x float>

define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) {
	%p = load %f8* %P		; <%f8> [#uses=1]
	%q = load %f8* %Q		; <%f8> [#uses=1]
	%R = add %f8 %p, %q		; <%f8> [#uses=1]
	store %f8 %R, %f8* %S
	ret void
}

into:

_test_f8:
	movaps	16(%rdi), %xmm0
	addps	16(%rsi), %xmm0
	movaps	(%rdi), %xmm1
	addps	(%rsi), %xmm1
	movaps	%xmm0, 16(%rdx)
	movaps	%xmm1, (%rdx)
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44725 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-12-08 23:24:26 +00:00
parent 697b53e0b2
commit 50187864c1
2 changed files with 27 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -281,6 +281,7 @@ private:
// Operand Vector Scalarization: <128 x ty> -> 2 x <64 x ty>.
bool SplitOperand(SDNode *N, unsigned OpNo);
SDOperand SplitOperand_STORE(StoreSDNode *N, unsigned OpNo);
};
} // end namespace llvm.

29
lib/CodeGen/SelectionDAG/LegalizeTypesSplit.cpp
View File

@ -172,11 +172,9 @@ bool DAGTypeLegalizer::SplitOperand(SDNode *N, unsigned OpNo) {
#endif
assert(0 && "Do not know how to split this operator's operand!");
abort();
#if 0
case ISD::STORE:
Res = ExpandOperand_STORE(cast<StoreSDNode>(N), OpNo);
Res = SplitOperand_STORE(cast<StoreSDNode>(N), OpNo);
break;
#endif
}
}
@ -200,3 +198,28 @@ bool DAGTypeLegalizer::SplitOperand(SDNode *N, unsigned OpNo) {
ReplaceValueWith(SDOperand(N, 0), Res);
return false;
}
SDOperand DAGTypeLegalizer::SplitOperand_STORE(StoreSDNode *N, unsigned OpNo) {
assert(OpNo == 1 && "Can only split the stored value");
SDOperand Ch = N->getChain();
SDOperand Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
unsigned Alignment = N->getAlignment();
bool isVol = N->isVolatile();
SDOperand Lo, Hi;
GetSplitOp(N->getOperand(1), Lo, Hi);
unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
// Increment the pointer to the other half.
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
getIntPtrConstant(IncrementSize));
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVol, MinAlign(Alignment, IncrementSize));
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
}