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AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions.
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196208 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5651,6 +5651,37 @@ defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
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int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
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i32, VPR128Lo, neon_uimm2_bare>;
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// Scalar general arithmetic operation
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class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
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Instruction INST>
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: Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
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class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
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Instruction INST>
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: Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(INST FPR64:$Rn, FPR64:$Rm)>;
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class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
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Instruction INST>
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: Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
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(v1f64 FPR64:$Ra))),
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(INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
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def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
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def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
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def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
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def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
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def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
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def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
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// Scalar Signed saturating doubling multiply returning
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// high half (scalar, by element)
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@ -118,3 +118,120 @@ define <2 x double> @sub2xdouble(<2 x double> %A, <2 x double> %B) {
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ret <2 x double> %tmp3
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}
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define <1 x double> @test_vadd_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vadd_f64
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; CHECK: fadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fadd <1 x double> %a, %b
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ret <1 x double> %1
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}
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define <1 x double> @test_vmul_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vmul_f64
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; CHECK: fmul d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fmul <1 x double> %a, %b
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ret <1 x double> %1
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}
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define <1 x double> @test_vdiv_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vdiv_f64
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; CHECK: fdiv d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fdiv <1 x double> %a, %b
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ret <1 x double> %1
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}
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define <1 x double> @test_vmla_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
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; CHECK-LABEL: test_vmla_f64
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; CHECK: fmul d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: fadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fmul <1 x double> %b, %c
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%2 = fadd <1 x double> %1, %a
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ret <1 x double> %2
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}
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define <1 x double> @test_vmls_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
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; CHECK-LABEL: test_vmls_f64
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; CHECK: fmul d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: fsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fmul <1 x double> %b, %c
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%2 = fsub <1 x double> %a, %1
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ret <1 x double> %2
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}
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define <1 x double> @test_vfms_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
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; CHECK-LABEL: test_vfms_f64
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; CHECK: fmsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fsub <1 x double> <double -0.000000e+00>, %b
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%2 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %1, <1 x double> %c, <1 x double> %a)
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ret <1 x double> %2
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}
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define <1 x double> @test_vfma_f64(<1 x double> %a, <1 x double> %b, <1 x double> %c) {
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; CHECK-LABEL: test_vfma_f64
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; CHECK: fmadd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = tail call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> %c, <1 x double> %a)
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ret <1 x double> %1
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}
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define <1 x double> @test_vsub_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vsub_f64
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; CHECK: fsub d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fsub <1 x double> %a, %b
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ret <1 x double> %1
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}
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define <1 x double> @test_vabd_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vabd_f64
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; CHECK: fabd d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = tail call <1 x double> @llvm.arm.neon.vabds.v1f64(<1 x double> %a, <1 x double> %b)
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ret <1 x double> %1
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}
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define <1 x double> @test_vmax_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vmax_f64
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; CHECK: fmax d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = tail call <1 x double> @llvm.arm.neon.vmaxs.v1f64(<1 x double> %a, <1 x double> %b)
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ret <1 x double> %1
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}
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define <1 x double> @test_vmin_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vmin_f64
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; CHECK: fmin d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = tail call <1 x double> @llvm.arm.neon.vmins.v1f64(<1 x double> %a, <1 x double> %b)
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ret <1 x double> %1
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}
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define <1 x double> @test_vmaxnm_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vmaxnm_f64
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; CHECK: fmaxnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = tail call <1 x double> @llvm.aarch64.neon.vmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
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ret <1 x double> %1
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}
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define <1 x double> @test_vminnm_f64(<1 x double> %a, <1 x double> %b) {
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; CHECK-LABEL: test_vminnm_f64
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; CHECK: fminnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%1 = tail call <1 x double> @llvm.aarch64.neon.vminnm.v1f64(<1 x double> %a, <1 x double> %b)
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ret <1 x double> %1
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}
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define <1 x double> @test_vabs_f64(<1 x double> %a) {
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; CHECK-LABEL: test_vabs_f64
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; CHECK: fabs d{{[0-9]+}}, d{{[0-9]+}}
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%1 = tail call <1 x double> @llvm.fabs.v1f64(<1 x double> %a)
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ret <1 x double> %1
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}
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define <1 x double> @test_vneg_f64(<1 x double> %a) {
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; CHECK-LABEL: test_vneg_f64
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; CHECK: fneg d{{[0-9]+}}, d{{[0-9]+}}
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%1 = fsub <1 x double> <double -0.000000e+00>, %a
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ret <1 x double> %1
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}
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declare <1 x double> @llvm.fabs.v1f64(<1 x double>)
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declare <1 x double> @llvm.aarch64.neon.vminnm.v1f64(<1 x double>, <1 x double>)
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declare <1 x double> @llvm.aarch64.neon.vmaxnm.v1f64(<1 x double>, <1 x double>)
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declare <1 x double> @llvm.arm.neon.vmins.v1f64(<1 x double>, <1 x double>)
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declare <1 x double> @llvm.arm.neon.vmaxs.v1f64(<1 x double>, <1 x double>)
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declare <1 x double> @llvm.arm.neon.vabds.v1f64(<1 x double>, <1 x double>)
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declare <1 x double> @llvm.fma.v1f64(<1 x double>, <1 x double>, <1 x double>)
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