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https://github.com/c64scene-ar/llvm-6502.git
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Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
2dd50e656f
commit
502e0aa628
@ -1694,13 +1694,19 @@ def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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}
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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// The assume-no-carry-in form uses the negation of the input since add/sub
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// assume opposite meanings of the carry flag (i.e., carry == !borrow).
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// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
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// details.
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def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
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(SUBri GPR:$src, so_imm_neg:$imm)>;
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//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
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// (SUBSri GPR:$src, so_imm_neg:$imm)>;
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//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
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// (SBCri GPR:$src, so_imm_neg:$imm)>;
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def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
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(SUBSri GPR:$src, so_imm_neg:$imm)>;
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// The with-carry-in form matches bitwise not instead of the negation.
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// Effectively, the inverse interpretation of the carry flag already accounts
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// for part of the negation.
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def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
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(SBCri GPR:$src, so_imm_not:$imm)>;
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// Note: These are implemented in C++ code, because they have to generate
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// ADD/SUBrs instructions, which use a complex pattern that a xform function
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@ -122,6 +122,10 @@ def imm0_255_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)(-N->getZExtValue()) < 255;
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}], imm_neg_XFORM>;
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def imm0_255_not : PatLeaf<(i32 imm), [{
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return (uint32_t)(~N->getZExtValue()) < 255;
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}], imm_comp_XFORM>;
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// Define Thumb2 specific addressing modes.
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// t2addrmode_imm12 := reg + imm12
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@ -1391,13 +1395,32 @@ defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
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BinOpFrag<(subc node:$LHS, node:$RHS)>>;
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// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
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// The assume-no-carry-in form uses the negation of the input since add/sub
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// assume opposite meanings of the carry flag (i.e., carry == !borrow).
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// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
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// details.
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// The AddedComplexity preferences the first variant over the others since
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// it can be shrunk to a 16-bit wide encoding, while the others cannot.
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let AddedComplexity = 1 in
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def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
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(t2SUBri GPR:$src, imm0_255_neg:$imm)>;
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def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
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(t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
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def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
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(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
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def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
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(t2SUBri GPR:$src, imm0_255_neg:$imm)>;
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def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
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(t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
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def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
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(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
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let AddedComplexity = 1 in
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def : T2Pat<(addc GPR:$src, imm0_255_neg:$imm),
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(t2SUBSri GPR:$src, imm0_255_neg:$imm)>;
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def : T2Pat<(addc GPR:$src, t2_so_imm_neg:$imm),
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(t2SUBSri GPR:$src, t2_so_imm_neg:$imm)>;
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// The with-carry-in form matches bitwise not instead of the negation.
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// Effectively, the inverse interpretation of the carry flag already accounts
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// for part of the negation.
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let AddedComplexity = 1 in
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def : T2Pat<(adde GPR:$src, imm0_255_not:$imm),
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(t2SBCSri GPR:$src, imm0_255_not:$imm)>;
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def : T2Pat<(adde GPR:$src, t2_so_imm_not:$imm),
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(t2SBCSri GPR:$src, t2_so_imm_not:$imm)>;
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// Select Bytes -- for disassembly only
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29
test/CodeGen/ARM/sub.ll
Normal file
29
test/CodeGen/ARM/sub.ll
Normal file
@ -0,0 +1,29 @@
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; RUN: llc -march=arm < %s | FileCheck %s
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; 171 = 0x000000ab
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define i64 @f1(i64 %a) {
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; CHECK: f1
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; CHECK: subs r0, r0, #171
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 171
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ret i64 %tmp
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}
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; 66846720 = 0x03fc0000
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define i64 @f2(i64 %a) {
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; CHECK: f2
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; CHECK: subs r0, r0, #255, 14
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; CHECK: sbc r1, r1, #0
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%tmp = sub i64 %a, 66846720
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ret i64 %tmp
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}
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; 734439407618 = 0x000000ab00000002
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define i64 @f3(i64 %a) {
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; CHECK: f3
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; CHECK: subs r0, r0, #2
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; CHECK: sbc r1, r1, #171
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%tmp = sub i64 %a, 734439407618
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ret i64 %tmp
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}
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@ -1,8 +1,54 @@
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; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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; RUN: llc -march=thumb -mattr=+thumb2 < %s | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK: f1:
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; CHECK: f1
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; CHECK: subs r0, r0, r2
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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; 734439407618 = 0x000000ab00000002
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define i64 @f2(i64 %a) {
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; CHECK: f2
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; CHECK: subs r0, #2
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; CHECK: sbc r1, r1, #171
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%tmp = sub i64 %a, 734439407618
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ret i64 %tmp
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}
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; 5066626890203138 = 0x0012001200000002
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define i64 @f3(i64 %a) {
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; CHECK: f3
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; CHECK: subs r0, #2
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; CHECK: sbc r1, r1, #1179666
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%tmp = sub i64 %a, 5066626890203138
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ret i64 %tmp
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}
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; 3747052064576897026 = 0x3400340000000002
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define i64 @f4(i64 %a) {
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; CHECK: f4
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; CHECK: subs r0, #2
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; CHECK: sbc r1, r1, #872428544
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%tmp = sub i64 %a, 3747052064576897026
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ret i64 %tmp
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}
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; 6221254862626095106 = 0x5656565600000002
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define i64 @f5(i64 %a) {
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; CHECK: f5
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; CHECK: subs r0, #2
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; CHECK: adc r1, r1, #-1448498775
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%tmp = sub i64 %a, 6221254862626095106
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ret i64 %tmp
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}
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; 287104476244869122 = 0x03fc000000000002
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define i64 @f6(i64 %a) {
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; CHECK: f6
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; CHECK: subs r0, #2
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; CHECK: sbc r1, r1, #66846720
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%tmp = sub i64 %a, 287104476244869122
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ret i64 %tmp
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}
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55
test/CodeGen/Thumb2/thumb2-sub3.ll
Normal file
55
test/CodeGen/Thumb2/thumb2-sub3.ll
Normal file
@ -0,0 +1,55 @@
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; RUN: llc -march=thumb -mattr=+thumb2 < %s | FileCheck %s
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; 171 = 0x000000ab
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define i64 @f1(i64 %a) {
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; CHECK: f1
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; CHECK: subs r0, #171
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; CHECK: adc r1, r1, #-1
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%tmp = sub i64 %a, 171
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ret i64 %tmp
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}
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; 1179666 = 0x00120012
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define i64 @f2(i64 %a) {
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; CHECK: f2
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; CHECK: subs.w r0, r0, #1179666
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; CHECK: adc r1, r1, #-1
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%tmp = sub i64 %a, 1179666
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ret i64 %tmp
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}
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; 872428544 = 0x34003400
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define i64 @f3(i64 %a) {
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; CHECK: f3
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; CHECK: subs.w r0, r0, #872428544
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; CHECK: adc r1, r1, #-1
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%tmp = sub i64 %a, 872428544
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ret i64 %tmp
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}
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; 1448498774 = 0x56565656
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define i64 @f4(i64 %a) {
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; CHECK: f4
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; CHECK: subs.w r0, r0, #1448498774
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; CHECK: adc r1, r1, #-1
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%tmp = sub i64 %a, 1448498774
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ret i64 %tmp
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}
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; 66846720 = 0x03fc0000
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define i64 @f5(i64 %a) {
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; CHECK: f5
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; CHECK: subs.w r0, r0, #66846720
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; CHECK: adc r1, r1, #-1
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%tmp = sub i64 %a, 66846720
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ret i64 %tmp
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}
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; 734439407618 = 0x000000ab00000002
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define i64 @f6(i64 %a) {
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; CHECK: f6
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; CHECK: subs r0, #2
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; CHECK: sbc r1, r1, #171
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%tmp = sub i64 %a, 734439407618
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ret i64 %tmp
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}
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