6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-29 10:32:47 +00:00
Code Issues Projects Releases Wiki Activity

Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209126 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Aaron Ballman 2014-05-19 14:29:04 +00:00
parent 29e068bac0
commit 50d09f1212
2 changed files with 6 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/ARM64/ARM64InstrInfo.cpp
View File

@ -827,14 +827,11 @@ bool ARM64InstrInfo::optimizeCompareInstr(
/// Return true if this is this instruction has a non-zero immediate
bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const {
switch (MI->getOpcode()) {
default:
if (MI->getOperand(3).isImm()) {
unsigned val = MI->getOperand(3).getImm();
return (val != 0);
}
break;
if (MI->getOperand(3).isImm()) {
unsigned val = MI->getOperand(3).getImm();
return (val != 0);
}
return false;
}

6
lib/Target/R600/AMDGPUMCInstLower.cpp
View File

@ -37,10 +37,8 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
{ }
enum AMDGPUMCInstLower::SISubtarget
AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
switch (Gen) {
default: return AMDGPUMCInstLower::SI;
}
AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const {
return AMDGPUMCInstLower::SI;
}
unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {