mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-21 02:24:22 +00:00
Revert "[DebugInfo] Add debug locations to constant SD nodes"
This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235987 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Jasper
@ -229,7 +229,7 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain,
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}
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RetOps[0] = Chain; // Update chain.
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RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
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RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
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// Add the flag if we have it.
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if (Flag.getNode())
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@ -261,7 +261,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
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// The second operand on the return instruction is the return address offset.
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// The return address is always %i7+8 with the 64-bit ABI.
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RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
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RetOps.push_back(DAG.getConstant(8, MVT::i32));
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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@ -289,7 +289,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain,
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// in the high bits of the register.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
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OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
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DAG.getConstant(32, DL, MVT::i32));
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DAG.getConstant(32, MVT::i32));
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// The next value may go in the low bits of the same register.
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// Handle both at once.
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@ -471,7 +471,7 @@ LowerFormalArguments_32(SDValue Chain,
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// Sparc is big endian, so add an offset based on the ObjectVT.
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unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
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FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
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DAG.getConstant(Offset, dl, MVT::i32));
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DAG.getConstant(Offset, MVT::i32));
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Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
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MachinePointerInfo(),
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VA.getValVT(), false, false, false,0);
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@ -570,7 +570,7 @@ LowerFormalArguments_64(SDValue Chain,
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// Get the high bits for i32 struct elements.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom())
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Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
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DAG.getConstant(32, DL, MVT::i32));
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DAG.getConstant(32, MVT::i32));
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// The caller promoted the argument, so insert an Assert?ext SDNode so we
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// won't promote the value again in this function.
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@ -723,7 +723,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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int FI = MFI->CreateStackObject(Size, Align, false);
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SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
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SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
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SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
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Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
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false, // isVolatile,
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@ -733,7 +733,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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ByValArgs.push_back(FIPtr);
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}
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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dl);
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SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
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@ -776,7 +776,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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assert(VA.needsCustom());
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// store SRet argument in %sp+64
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
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SDValue PtrOff = DAG.getIntPtrConstant(64);
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PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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MachinePointerInfo(),
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@ -793,7 +793,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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// if it is double-word aligned, just store.
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if (Offset % 8 == 0) {
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
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SDValue PtrOff = DAG.getIntPtrConstant(Offset);
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PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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MachinePointerInfo(),
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@ -811,7 +811,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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MachinePointerInfo(), false, false, false, 0);
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// Increment the pointer to the other half.
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StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
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DAG.getIntPtrConstant(4, dl));
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DAG.getIntPtrConstant(4));
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// Load the low part.
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SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
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MachinePointerInfo(), false, false, false, 0);
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@ -826,7 +826,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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// Store the low part in stack.
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unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
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SDValue PtrOff = DAG.getIntPtrConstant(Offset);
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PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
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MachinePointerInfo(),
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@ -836,13 +836,13 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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unsigned Offset = VA.getLocMemOffset() + StackOffset;
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// Store the high part.
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
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SDValue PtrOff = DAG.getIntPtrConstant(Offset);
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PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
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MachinePointerInfo(),
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false, false, 0));
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// Store the low part.
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PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
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PtrOff = DAG.getIntPtrConstant(Offset+4);
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PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
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MachinePointerInfo(),
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@ -867,8 +867,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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// Create a store off the stack pointer for this argument.
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
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dl);
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SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
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PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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MachinePointerInfo(),
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@ -910,7 +909,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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if (hasStructRetAttr)
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Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
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Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
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RegsToPass[i].second.getValueType()));
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@ -930,8 +929,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
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DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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DAG.getIntPtrConstant(0, true), InFlag, dl);
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InFlag = Chain.getValue(1);
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// Assign locations to each value returned by this call.
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@ -1083,7 +1082,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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// Adjust the stack pointer to make room for the arguments.
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// FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
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// with more than 6 arguments.
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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DL);
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// Collect the set of registers to pass to the function and their values.
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@ -1131,10 +1130,10 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
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unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
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SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
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SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
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SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset);
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HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
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HiPtrOff);
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SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
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SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8);
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LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
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LoPtrOff);
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@ -1160,7 +1159,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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// passed in the high bits of the register.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
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Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
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DAG.getConstant(32, DL, MVT::i32));
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DAG.getConstant(32, MVT::i32));
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// The next value may go in the low bits of the same register.
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// Handle both at once.
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@ -1185,7 +1184,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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// %sp+BIAS+128 in ours.
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SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
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Subtarget->getStackPointerBias() +
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128, DL);
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128);
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PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
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MachinePointerInfo(),
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@ -1248,8 +1247,8 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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InGlue = Chain.getValue(1);
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// Revert the stack pointer immediately after the call.
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
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DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
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DAG.getIntPtrConstant(0, true), InGlue, DL);
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InGlue = Chain.getValue(1);
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// Now extract the return values. This is more or less the same as
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@ -1290,7 +1289,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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// Get the high bits for i32 struct elements.
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if (VA.getValVT() == MVT::i32 && VA.needsCustom())
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RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
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DAG.getConstant(32, DL, MVT::i32));
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DAG.getConstant(32, MVT::i32));
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// The callee promoted the return value, so insert an Assert?ext SDNode so
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// we won't promote the value again in this function.
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@ -1832,7 +1831,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
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// abs44.
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SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
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SparcMCExpr::VK_Sparc_M44, DAG);
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H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
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H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
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SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
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L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
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return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
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@ -1841,7 +1840,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
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// abs64.
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SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
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SparcMCExpr::VK_Sparc_HM, DAG);
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Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
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Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
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SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
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SparcMCExpr::VK_Sparc_LO, DAG);
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return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
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@ -1896,7 +1895,7 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
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SDValue Chain = DAG.getEntryNode();
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SDValue InFlag;
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL);
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
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Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
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InFlag = Chain.getValue(1);
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SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
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@ -1915,8 +1914,8 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
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Ops.push_back(InFlag);
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Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),
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DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
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Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
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DAG.getIntPtrConstant(0, true), InFlag, DL);
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InFlag = Chain.getValue(1);
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SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
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@ -2099,54 +2098,54 @@ SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
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switch(SPCC) {
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default: {
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SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UL : {
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SDValue Mask = DAG.getTargetConstant(1, DL, Result.getValueType());
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SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
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Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
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SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_ULE: {
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SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UG : {
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SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
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SPCC = SPCC::ICC_G;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UGE: {
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SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_U : {
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SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
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SPCC = SPCC::ICC_E;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_O : {
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SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_LG : {
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SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
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SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
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Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
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SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_NE;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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case SPCC::FCC_UE : {
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SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType());
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SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
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Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
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SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
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SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
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SPCC = SPCC::ICC_E;
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return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
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}
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@ -2318,7 +2317,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
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}
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}
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return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
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DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
|
||||
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
|
||||
}
|
||||
|
||||
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
|
||||
@ -2354,7 +2353,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
|
||||
}
|
||||
}
|
||||
return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
|
||||
DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
|
||||
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
|
||||
}
|
||||
|
||||
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
|
||||
@ -2371,7 +2370,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
|
||||
SDValue Offset =
|
||||
DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
|
||||
DAG.getRegister(SP::I6, TLI.getPointerTy()),
|
||||
DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
|
||||
DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
|
||||
MachinePointerInfo(SV), false, false, 0);
|
||||
@ -2389,8 +2388,7 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
|
||||
MachinePointerInfo(SV), false, false, false, 0);
|
||||
// Increment the pointer, VAList, to the next vaarg.
|
||||
SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
|
||||
DAG.getIntPtrConstant(VT.getSizeInBits()/8,
|
||||
DL));
|
||||
DAG.getIntPtrConstant(VT.getSizeInBits()/8));
|
||||
// Store the incremented VAList to the legalized pointer.
|
||||
InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
|
||||
VAListPtr, MachinePointerInfo(SV), false, false, 0);
|
||||
@ -2419,7 +2417,7 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
|
||||
regSpillArea += Subtarget->getStackPointerBias();
|
||||
|
||||
SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
|
||||
DAG.getConstant(regSpillArea, dl, VT));
|
||||
DAG.getConstant(regSpillArea, VT));
|
||||
SDValue Ops[2] = { NewVal, Chain };
|
||||
return DAG.getMergeValues(Ops, dl);
|
||||
}
|
||||
@ -2448,7 +2446,7 @@ static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
|
||||
FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
|
||||
if (Subtarget->is64Bit())
|
||||
FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
|
||||
DAG.getIntPtrConstant(stackBias, dl));
|
||||
DAG.getIntPtrConstant(stackBias));
|
||||
return FrameAddr;
|
||||
}
|
||||
|
||||
@ -2460,13 +2458,13 @@ static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
|
||||
|
||||
while (depth--) {
|
||||
SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
|
||||
DAG.getIntPtrConstant(Offset, dl));
|
||||
DAG.getIntPtrConstant(Offset));
|
||||
FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
|
||||
false, false, false, 0);
|
||||
}
|
||||
if (Subtarget->is64Bit())
|
||||
FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
|
||||
DAG.getIntPtrConstant(stackBias, dl));
|
||||
DAG.getIntPtrConstant(stackBias));
|
||||
return FrameAddr;
|
||||
}
|
||||
|
||||
@ -2509,7 +2507,7 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
|
||||
SDValue Ptr = DAG.getNode(ISD::ADD,
|
||||
dl, VT,
|
||||
FrameAddr,
|
||||
DAG.getIntPtrConstant(Offset, dl));
|
||||
DAG.getIntPtrConstant(Offset));
|
||||
RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
|
||||
MachinePointerInfo(), false, false, false, 0);
|
||||
|
||||
@ -2565,7 +2563,7 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
|
||||
EVT addrVT = LdNode->getBasePtr().getValueType();
|
||||
SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
|
||||
LdNode->getBasePtr(),
|
||||
DAG.getConstant(8, dl, addrVT));
|
||||
DAG.getConstant(8, addrVT));
|
||||
SDValue Lo64 = DAG.getLoad(MVT::f64,
|
||||
dl,
|
||||
LdNode->getChain(),
|
||||
@ -2573,8 +2571,8 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
|
||||
LdNode->getPointerInfo(),
|
||||
false, false, false, alignment);
|
||||
|
||||
SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
|
||||
SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
|
||||
SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
|
||||
SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
|
||||
|
||||
SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
|
||||
dl, MVT::f128);
|
||||
@ -2601,8 +2599,8 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
|
||||
StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
|
||||
assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
|
||||
&& "Unexpected node type");
|
||||
SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
|
||||
SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
|
||||
SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
|
||||
SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
|
||||
|
||||
SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
|
||||
dl,
|
||||
@ -2629,7 +2627,7 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
|
||||
EVT addrVT = StNode->getBasePtr().getValueType();
|
||||
SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
|
||||
StNode->getBasePtr(),
|
||||
DAG.getConstant(8, dl, addrVT));
|
||||
DAG.getConstant(8, addrVT));
|
||||
OutChains[1] = DAG.getStore(StNode->getChain(),
|
||||
dl,
|
||||
SDValue(Lo64, 0),
|
||||
@ -2680,13 +2678,13 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
|
||||
SDValue Src1 = Op.getOperand(0);
|
||||
SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
|
||||
SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
|
||||
DAG.getConstant(32, dl, MVT::i64));
|
||||
DAG.getConstant(32, MVT::i64));
|
||||
Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
|
||||
|
||||
SDValue Src2 = Op.getOperand(1);
|
||||
SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
|
||||
SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
|
||||
DAG.getConstant(32, dl, MVT::i64));
|
||||
DAG.getConstant(32, MVT::i64));
|
||||
Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
|
||||
|
||||
|
||||
@ -2713,7 +2711,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
|
||||
Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
|
||||
Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
|
||||
Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
|
||||
DAG.getConstant(32, dl, MVT::i64));
|
||||
DAG.getConstant(32, MVT::i64));
|
||||
|
||||
SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
|
||||
SDValue Ops[2] = { Dst, Carry };
|
||||
@ -2737,7 +2735,7 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
|
||||
if (LHS.getValueType() != VT)
|
||||
return Op;
|
||||
|
||||
SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
|
||||
SDValue ShiftAmt = DAG.getConstant(63, VT);
|
||||
|
||||
SDValue RHS = Op.getOperand(1);
|
||||
SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
|
||||
@ -2748,14 +2746,14 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
|
||||
RTLIB::MUL_I128, WideVT,
|
||||
Args, 4, isSigned, dl).first;
|
||||
SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
|
||||
MulResult, DAG.getIntPtrConstant(0, dl));
|
||||
MulResult, DAG.getIntPtrConstant(0));
|
||||
SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
|
||||
MulResult, DAG.getIntPtrConstant(1, dl));
|
||||
MulResult, DAG.getIntPtrConstant(1));
|
||||
if (isSigned) {
|
||||
SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
|
||||
TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
|
||||
} else {
|
||||
TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
|
||||
TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT),
|
||||
ISD::SETNE);
|
||||
}
|
||||
// MulResult is a node with an illegal type. Because such things are not
|
||||
@ -3121,8 +3119,7 @@ LowerAsmOperandForConstraint(SDValue Op,
|
||||
case 'I':
|
||||
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
|
||||
if (isInt<13>(C->getSExtValue())) {
|
||||
Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
|
||||
Op.getValueType());
|
||||
Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
|
||||
break;
|
||||
}
|
||||
return;
|
||||
|
||||
Reference in New Issue
Block a user