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DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)

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A common idiom is to use zero and all-ones as sentinal values and to
check for both in a single conditional ("x != 0 && x != (unsigned)-1").
That generates code, for i32, like:
  testl %edi, %edi
  setne %al
  cmpl  $-1, %edi
  setne %cl
  andb  %al, %cl

With this transform, we generate the simpler:
  incl  %edi
  cmpl  $1, %edi
  seta  %al

Similar improvements for other integer sizes and on other platforms. In
general, combining the two setcc instructions into one is better.

rdar://14689217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188315 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2013-08-13 21:30:58 +00:00
parent af9e355755
commit 51a0280d29
3 changed files with 40 additions and 0 deletions
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13
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2675,6 +2675,19 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
}
}
// Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
Op0 == Op1 && LL.getValueType().isInteger() &&
Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
(cast<ConstantSDNode>(LR)->isAllOnesValue() &&
cast<ConstantSDNode>(RR)->isNullValue()))) {
SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
LL, DAG.getConstant(1, LL.getValueType()));
AddToWorkList(ADDNode.getNode());
return DAG.getSetCC(SDLoc(N), VT, ADDNode,
DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
}
// canonicalize equivalent to ll == rl
if (LL == RR && LR == RL) {
Op1 = ISD::getSetCCSwappedOperands(Op1);

14
test/CodeGen/ARM/setcc-sentinals.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s
define zeroext i1 @test0(i32 %x) nounwind {
; CHECK-LABEL: test0:
; CHECK-NEXT: add [[REG:(r[0-9]+)|(lr)]], r0, #1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: cmp [[REG]], #1
; CHECK-NEXT: movhi r0, #1
; CHECK-NEXT: bx lr
%cmp1 = icmp ne i32 %x, -1
%not.cmp = icmp ne i32 %x, 0
%.cmp1 = and i1 %cmp1, %not.cmp
ret i1 %.cmp1
}

13
test/CodeGen/X86/setcc-sentinals.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc < %s -mcpu=generic -march=x86-64 -asm-verbose=false | FileCheck %s
define zeroext i1 @test0(i64 %x) nounwind {
; CHECK-LABEL: test0:
; CHECK-NEXT: incq %rdi
; CHECK-NEXT: cmpq $1, %rdi
; CHECK-NEXT: seta %al
; CHECK-NEXT: ret
%cmp1 = icmp ne i64 %x, -1
%not.cmp = icmp ne i64 %x, 0
%.cmp1 = and i1 %cmp1, %not.cmp
ret i1 %.cmp1
}