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Allow AVX vrsqrtps generation.

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This is a follow-on to r220570 that allows a 256-bit (v8f32)
version of vrsqrtps to be generated.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220579 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2014-10-24 17:59:18 +00:00
parent 7f6ba1758b
commit 51fa1bcef3
2 changed files with 30 additions and 8 deletions
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5
lib/Target/X86/X86ISelLowering.cpp
View File

@ -14383,13 +14383,14 @@ SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
EVT VT = Op.getValueType();
// SSE1 has rsqrtss and rsqrtps.
// TODO: Add support for AVX (v8f32) and AVX512 (v16f32).
// TODO: Add support for AVX512 (v16f32).
// It is likely not profitable to do this for f64 because a double-precision
// rsqrt estimate with refinement on x86 prior to FMA requires at least 16
// instructions: convert to single, rsqrtss, convert back to double, refine
// (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
// along with FMA, this could be a throughput win.
if (Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) {
if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
(Subtarget->hasAVX() && VT == MVT::v8f32)) {
RefinementSteps = 1;
UseOneConstNR = false;
return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);

33
test/CodeGen/X86/sqrt-fastmath.ll
View File

@ -55,9 +55,14 @@ entry:
declare x86_fp80 @__sqrtl_finite(x86_fp80) #1
declare float @llvm.sqrt.f32(float) #1
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #1
; If the target's sqrtss and divss instructions are substantially
; slower than rsqrtss with a Newton-Raphson refinement, we should
; generate the estimate sequence.
define float @reciprocal_square_root(float %x) #0 {
%sqrt = tail call float @llvm.sqrt.f32(float %x)
%div = fdiv fast float 1.0, %sqrt
@ -78,11 +83,6 @@ define float @reciprocal_square_root(float %x) #0 {
; BTVER2-NEXT: retq
}
declare float @llvm.sqrt.f32(float) #1
; If the target's sqrtps and divps instructions are substantially
; slower than rsqrtps with a Newton-Raphson refinement, we should
; generate the estimate sequence.
define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 {
%sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
@ -103,7 +103,28 @@ define <4 x float> @reciprocal_square_root_v4f32(<4 x float> %x) #0 {
; BTVER2-NEXT: retq
}
declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1
define <8 x float> @reciprocal_square_root_v8f32(<8 x float> %x) #0 {
%sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
ret <8 x float> %div
; CHECK-LABEL: reciprocal_square_root_v8f32:
; CHECK: sqrtps
; CHECK-NEXT: sqrtps
; CHECK-NEXT: movaps
; CHECK-NEXT: movaps
; CHECK-NEXT: divps
; CHECK-NEXT: divps
; CHECK-NEXT: retq
; BTVER2-LABEL: reciprocal_square_root_v8f32:
; BTVER2: vrsqrtps
; BTVER2-NEXT: vmulps
; BTVER2-NEXT: vmulps
; BTVER2-NEXT: vmulps
; BTVER2-NEXT: vaddps
; BTVER2-NEXT: vmulps
; BTVER2-NEXT: retq
}
attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "use-soft-float"="false" }