mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-08 09:43:20 +00:00
[X86][SchedModel] Fixed some wrong scheduling model found by code inspection.
Source: Agner Fog's Instruction tables. Related to <rdar://problem/15607571> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214940 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
parent
8480beefd0
commit
5200d84bdc
@ -38,12 +38,17 @@ def MMX_PHADDSUBD : OpndItins<
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>;
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}
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let Sched = WriteVecLogic in
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def MMX_INTALU_ITINS_VECLOGICSCHED : OpndItins<
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IIC_MMX_ALU_RR, IIC_MMX_ALU_RM
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>;
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let Sched = WriteVecIMul in
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def MMX_PMUL_ITINS : OpndItins<
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IIC_MMX_PMUL, IIC_MMX_PMUL
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>;
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let Sched = WriteVecALU in {
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let Sched = WriteVecIMul in {
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def MMX_PSADBW_ITINS : OpndItins<
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IIC_MMX_PSADBW, IIC_MMX_PSADBW
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>;
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@ -167,12 +172,14 @@ multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
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def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
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Sched<[WriteShuffle]>;
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def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
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(bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>,
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Sched<[WriteShuffleLd, ReadAfterLd]>;
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}
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multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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@ -427,13 +434,13 @@ let Constraints = "$src1 = $dst" in
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
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MMX_INTALU_ITINS, 1>;
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MMX_INTALU_ITINS_VECLOGICSCHED, 1>;
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defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
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MMX_INTALU_ITINS, 1>;
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MMX_INTALU_ITINS_VECLOGICSCHED, 1>;
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defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
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MMX_INTALU_ITINS, 1>;
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MMX_INTALU_ITINS_VECLOGICSCHED, 1>;
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defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
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MMX_INTALU_ITINS>;
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MMX_INTALU_ITINS_VECLOGICSCHED>;
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// Shift Instructions
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defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
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@ -181,6 +181,7 @@ def SSE_MPSADBW_ITINS : OpndItins<
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IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
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>;
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let Sched = WriteVecIMul in
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def SSE_PMULLD_ITINS : OpndItins<
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IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
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>;
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@ -218,11 +219,21 @@ def DEFAULT_ITINS_BLENDSCHED : OpndItins<
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IIC_ALU_NONMEM, IIC_ALU_MEM
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>;
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let Sched = WriteVarBlend in
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def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
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IIC_ALU_NONMEM, IIC_ALU_MEM
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>;
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let Sched = WriteFBlend in
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def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
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IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
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>;
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let Sched = WriteBlend in
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def SSE_INTALU_ITINS_BLEND_P : OpndItins<
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IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
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>;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 Instructions Classes
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//===----------------------------------------------------------------------===//
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@ -7308,7 +7319,7 @@ let Constraints = "$src1 = $dst" in {
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let Predicates = [HasAVX] in {
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defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
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memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
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memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
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VEX_4V;
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defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
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memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
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@ -7316,7 +7327,7 @@ let Predicates = [HasAVX] in {
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}
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let Predicates = [HasAVX2] in {
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defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
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memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
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memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
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VEX_4V, VEX_L;
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defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
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memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
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@ -7422,7 +7433,7 @@ let Constraints = "$src1 = $dst" in {
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1, SSE_INTALU_ITINS_FBLEND_P>;
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defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
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VR128, memopv2i64, i128mem,
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1, SSE_INTALU_ITINS_FBLEND_P>;
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1, SSE_INTALU_ITINS_BLEND_P>;
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defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
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VR128, memopv2i64, i128mem,
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1, SSE_MPSADBW_ITINS>;
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@ -7555,7 +7566,7 @@ let Uses = [XMM0], Constraints = "$src1 = $dst" in {
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!strconcat(OpcodeStr,
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"\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
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itins.rr>;
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itins.rr>, Sched<[itins.Sched]>;
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def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, x86memop:$src2),
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@ -7564,18 +7575,21 @@ let Uses = [XMM0], Constraints = "$src1 = $dst" in {
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[(set VR128:$dst,
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(IntId VR128:$src1,
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(bitconvert (mem_frag addr:$src2)), XMM0))],
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itins.rm>;
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itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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let ExeDomain = SSEPackedDouble in
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defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
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int_x86_sse41_blendvpd>;
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int_x86_sse41_blendvpd,
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DEFAULT_ITINS_FBLENDSCHED>;
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let ExeDomain = SSEPackedSingle in
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defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
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int_x86_sse41_blendvps>;
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int_x86_sse41_blendvps,
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DEFAULT_ITINS_FBLENDSCHED>;
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defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
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int_x86_sse41_pblendvb>;
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int_x86_sse41_pblendvb,
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DEFAULT_ITINS_VARBLENDSCHED>;
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// Aliases with the implicit xmm0 argument
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def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
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@ -8763,14 +8777,14 @@ let Predicates = [HasAVX] in {
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//
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multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
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ValueType OpVT> {
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ValueType OpVT, X86FoldableSchedWrite Sched> {
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def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
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Sched<[WriteFShuffle256]>, VEX_4V, VEX_L;
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Sched<[Sched]>, VEX_4V, VEX_L;
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def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, i256mem:$src2),
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!strconcat(OpcodeStr,
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@ -8778,22 +8792,22 @@ multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
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[(set VR256:$dst,
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(OpVT (X86VPermv VR256:$src1,
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(bitconvert (mem_frag addr:$src2)))))]>,
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Sched<[WriteFShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
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Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
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}
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defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32>;
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defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
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let ExeDomain = SSEPackedSingle in
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defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32>;
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defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
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multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
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ValueType OpVT> {
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ValueType OpVT, X86FoldableSchedWrite Sched> {
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def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR256:$dst,
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(OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
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Sched<[WriteShuffle256]>, VEX, VEX_L;
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Sched<[Sched]>, VEX, VEX_L;
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def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
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(ins i256mem:$src1, i8imm:$src2),
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!strconcat(OpcodeStr,
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@ -8801,12 +8815,14 @@ multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
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[(set VR256:$dst,
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(OpVT (X86VPermi (mem_frag addr:$src1),
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(i8 imm:$src2))))]>,
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Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX, VEX_L;
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Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
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}
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defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64>, VEX_W;
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defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
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WriteShuffle256>, VEX_W;
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let ExeDomain = SSEPackedDouble in
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defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64>, VEX_W;
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defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
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WriteFShuffle256>, VEX_W;
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//===----------------------------------------------------------------------===//
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// VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
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