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fit in 80 cols

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74270 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-06-26 05:39:02 +00:00
parent b8b7347c10
commit 5202312d2e
1 changed files with 4 additions and 5 deletions
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9
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
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@ -30,10 +30,9 @@ using namespace llvm;
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
/// implicit physical register output.
void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
bool IsClone, bool IsCloned,
unsigned SrcReg,
DenseMap<SDValue, unsigned> &VRBaseMap) {
void ScheduleDAGSDNodes::
EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
// Just use the input register directly!
@ -335,7 +334,7 @@ getSuperRegisterRegClass(const TargetRegisterClass *TRC,
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
DenseMap<SDValue, unsigned> &VRBaseMap) {
DenseMap<SDValue, unsigned> &VRBaseMap){
unsigned VRBase = 0;
unsigned Opc = Node->getMachineOpcode();