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Simplify the loop a bit

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-10-05 03:45:44 +00:00
parent 92581c24a3
commit 521c16aadd
1 changed files with 9 additions and 10 deletions
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19
lib/Transforms/Utils/PromoteMemoryToRegister.cpp
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@ -193,6 +193,7 @@ bool PromoteMem2Reg::QueuePhiNode(BasicBlock *BB, unsigned AllocaNo) {
void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred, void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
std::vector<Value*> &IncomingVals) { std::vector<Value*> &IncomingVals) {
// If this BB needs a PHI node, update the PHI node for each variable we need // If this BB needs a PHI node, update the PHI node for each variable we need
// PHI nodes for. // PHI nodes for.
std::map<BasicBlock*, std::vector<PHINode *> >::iterator std::map<BasicBlock*, std::vector<PHINode *> >::iterator
@ -220,8 +221,7 @@ void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
// mark as visited // mark as visited
Visited.insert(BB); Visited.insert(BB);
BasicBlock::iterator II = BB->begin(); for (BasicBlock::iterator II = BB->begin(); !isa<TerminatorInst>(II); ) {
while (1) {
Instruction *I = II++; // get the instruction, increment iterator Instruction *I = II++; // get the instruction, increment iterator
if (LoadInst *LI = dyn_cast<LoadInst>(I)) { if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
@ -246,16 +246,15 @@ void PromoteMem2Reg::RenamePass(BasicBlock *BB, BasicBlock *Pred,
BB->getInstList().erase(SI); BB->getInstList().erase(SI);
} }
} }
} else if (TerminatorInst *TI = dyn_cast<TerminatorInst>(I)) {
// Recurse across our successors
for (unsigned i = 0; i != TI->getNumSuccessors(); i++) {
std::vector<Value*> OutgoingVals(IncomingVals);
RenamePass(TI->getSuccessor(i), BB, OutgoingVals);
}
break;
} }
} }
// Recurse to our successors
TerminatorInst *TI = BB->getTerminator();
for (unsigned i = 0; i != TI->getNumSuccessors(); i++) {
std::vector<Value*> OutgoingVals(IncomingVals);
RenamePass(TI->getSuccessor(i), BB, OutgoingVals);
}
} }
/// PromoteMemToReg - Promote the specified list of alloca instructions into /// PromoteMemToReg - Promote the specified list of alloca instructions into