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[FastISel][AArch64] Follow-up fix for "Fix shift-immediate emission for "zero" shifts."

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Shifts also perform sign-/zero-extends to larger types, which requires us to emit
an integer extend instead of a simple COPY.

Related to PR21594.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222257 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-11-18 21:20:17 +00:00
parent a140448780
commit 52e0f75f82
2 changed files with 50 additions and 17 deletions
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43
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -3886,7 +3886,7 @@ unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
bool Op0IsKill, uint64_t Shift,
bool IsZext) {
bool IsZExt) {
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
"Unexpected source/return type pair.");
assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
@ -3904,11 +3904,14 @@ unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
// Just emit a copy for "zero" shifts.
if (Shift == 0) {
unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(Op0, getKillRegState(Op0IsKill));
return ResultReg;
if (RetVT == SrcVT) {
unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(Op0, getKillRegState(Op0IsKill));
return ResultReg;
} else
return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
}
// Don't deal with undefined shifts.
@ -3947,7 +3950,7 @@ unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
{AArch64::SBFMWri, AArch64::SBFMXri},
{AArch64::UBFMWri, AArch64::UBFMXri}
};
unsigned Opc = OpcTable[IsZext][Is64Bit];
unsigned Opc = OpcTable[IsZExt][Is64Bit];
if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
unsigned TmpReg = MRI.createVirtualRegister(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
@ -4007,11 +4010,14 @@ unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
// Just emit a copy for "zero" shifts.
if (Shift == 0) {
unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(Op0, getKillRegState(Op0IsKill));
return ResultReg;
if (RetVT == SrcVT) {
unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(Op0, getKillRegState(Op0IsKill));
return ResultReg;
} else
return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
}
// Don't deal with undefined shifts.
@ -4124,11 +4130,14 @@ unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
// Just emit a copy for "zero" shifts.
if (Shift == 0) {
unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(Op0, getKillRegState(Op0IsKill));
return ResultReg;
if (RetVT == SrcVT) {
unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), ResultReg)
.addReg(Op0, getKillRegState(Op0IsKill));
return ResultReg;
} else
return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
}
// Don't deal with undefined shifts.

24
test/CodeGen/AArch64/fast-isel-shift.ll
View File

@ -427,3 +427,27 @@ define i32 @ashr_zero(i32 %a) {
ret i32 %1
}
; CHECK-LABEL: shl_zext_zero
; CHECK: ubfx x0, x0, #0, #32
define i64 @shl_zext_zero(i32 %a) {
%1 = zext i32 %a to i64
%2 = shl i64 %1, 0
ret i64 %2
}
; CHECK-LABEL: lshr_zext_zero
; CHECK: ubfx x0, x0, #0, #32
define i64 @lshr_zext_zero(i32 %a) {
%1 = zext i32 %a to i64
%2 = lshr i64 %1, 0
ret i64 %2
}
; CHECK-LABEL: ashr_zext_zero
; CHECK: ubfx x0, x0, #0, #32
define i64 @ashr_zext_zero(i32 %a) {
%1 = zext i32 %a to i64
%2 = ashr i64 %1, 0
ret i64 %2
}