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https://github.com/c64scene-ar/llvm-6502.git
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Change getCopyToParts and getCopyFromParts to always use target-endian
register ordering, for both physical and virtual registers. Update the PPC target lowering for calls to expect registers for the call result to already be in target order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
parent
4d6f96d699
commit
532dc2e1f2
@ -621,7 +621,6 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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unsigned NumParts,
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MVT::ValueType PartVT,
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MVT::ValueType ValueVT,
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bool EndianOrder,
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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if (!MVT::isVector(ValueVT) || NumParts == 1) {
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SDOperand Val = Parts[0];
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@ -631,7 +630,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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assert(NumParts == 2 &&
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"Cannot expand to more than 2 elts yet!");
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SDOperand Hi = Parts[1];
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if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian())
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if (!DAG.getTargetLoweringInfo().isLittleEndian())
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std::swap(Val, Hi);
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return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
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}
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@ -692,7 +691,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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// as appropriate.
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for (unsigned i = 0; i != NumParts; ++i)
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Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
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PartVT, IntermediateVT, EndianOrder);
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PartVT, IntermediateVT);
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} else if (NumParts > 0) {
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// If the intermediate type was expanded, build the intermediate operands
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// from the parts.
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@ -701,7 +700,7 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
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unsigned Factor = NumIntermediates / NumParts;
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for (unsigned i = 0; i != NumIntermediates; ++i)
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Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
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PartVT, IntermediateVT, EndianOrder);
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PartVT, IntermediateVT);
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}
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// Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
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@ -718,8 +717,7 @@ static void getCopyToParts(SelectionDAG &DAG,
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SDOperand Val,
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SDOperand *Parts,
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unsigned NumParts,
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MVT::ValueType PartVT,
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bool EndianOrder) {
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MVT::ValueType PartVT) {
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MVT::ValueType ValueVT = Val.getValueType();
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if (!MVT::isVector(ValueVT) || NumParts == 1) {
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@ -728,7 +726,7 @@ static void getCopyToParts(SelectionDAG &DAG,
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for (unsigned i = 0; i != NumParts; ++i)
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Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
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DAG.getConstant(i, MVT::i32));
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if (EndianOrder && !DAG.getTargetLoweringInfo().isLittleEndian())
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if (!DAG.getTargetLoweringInfo().isLittleEndian())
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std::reverse(Parts, Parts + NumParts);
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return;
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}
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@ -789,7 +787,7 @@ static void getCopyToParts(SelectionDAG &DAG,
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// If the register was not expanded, promote or copy the value,
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// as appropriate.
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for (unsigned i = 0; i != NumParts; ++i)
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getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT, EndianOrder);
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getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
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} else if (NumParts > 0) {
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// If the intermediate type was expanded, split each the value into
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// legal parts.
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@ -797,7 +795,7 @@ static void getCopyToParts(SelectionDAG &DAG,
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"Must expand into a divisible number of parts!");
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unsigned Factor = NumParts / NumIntermediates;
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for (unsigned i = 0; i != NumIntermediates; ++i)
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getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT, EndianOrder);
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getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
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}
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}
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@ -928,7 +926,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
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unsigned NumParts = TLI.getNumRegisters(VT);
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MVT::ValueType PartVT = TLI.getRegisterType(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, true);
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getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
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for (unsigned i = 0; i < NumParts; ++i) {
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NewValues.push_back(Parts[i]);
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NewValues.push_back(DAG.getConstant(false, MVT::i32));
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@ -2952,11 +2950,6 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
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/// If the Flag pointer is NULL, no flag is used.
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SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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SDOperand &Chain, SDOperand *Flag)const{
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// Get the list of registers, in the appropriate order.
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std::vector<unsigned> R(Regs);
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if (!DAG.getTargetLoweringInfo().isLittleEndian())
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std::reverse(R.begin(), R.end());
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// Copy the legal parts from the registers.
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unsigned NumParts = Regs.size();
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SmallVector<SDOperand, 8> Parts(NumParts);
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@ -2971,7 +2964,7 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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}
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// Assemble the legal parts into the final value.
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return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT, false);
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return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
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}
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/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
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@ -2980,21 +2973,16 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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/// If the Flag pointer is NULL, no flag is used.
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void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
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SDOperand &Chain, SDOperand *Flag) const {
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// Get the list of registers, in the appropriate order.
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std::vector<unsigned> R(Regs);
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if (!DAG.getTargetLoweringInfo().isLittleEndian())
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std::reverse(R.begin(), R.end());
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// Get the list of the values's legal parts.
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unsigned NumParts = Regs.size();
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SmallVector<SDOperand, 8> Parts(NumParts);
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getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT, false);
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getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
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// Copy the parts into the registers.
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for (unsigned i = 0; i != NumParts; ++i) {
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SDOperand Part = Flag ?
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DAG.getCopyToReg(Chain, R[i], Parts[i], *Flag) :
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DAG.getCopyToReg(Chain, R[i], Parts[i]);
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DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
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DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
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Chain = Part.getValue(0);
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if (Flag)
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*Flag = Part.getValue(1);
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@ -3867,7 +3855,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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SmallVector<SDOperand, 4> Parts(NumParts);
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for (unsigned j = 0; j != NumParts; ++j)
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Parts[j] = SDOperand(Result, i++);
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Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, true));
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Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
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break;
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}
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}
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@ -3939,7 +3927,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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MVT::ValueType PartVT = getRegisterType(VT);
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unsigned NumParts = getNumRegisters(VT);
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SmallVector<SDOperand, 4> Parts(NumParts);
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getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, true);
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getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
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for (unsigned i = 0; i != NumParts; ++i) {
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// if it isn't first piece, alignment must be 1
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unsigned MyFlags = Flags;
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@ -3979,7 +3967,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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SmallVector<SDOperand, 4> Results(NumRegs);
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for (unsigned i = 0; i != NumRegs; ++i)
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Results[i] = Res.getValue(i);
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Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, false, AssertOp);
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Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
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}
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return std::make_pair(Res, Chain);
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@ -4269,7 +4257,7 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
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SmallVector<SDOperand, 8> Chains(NumRegs);
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// Copy the value by legal parts into sequential virtual registers.
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getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT, false);
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getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
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for (unsigned i = 0; i != NumRegs; ++i)
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Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
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return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
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@ -4406,8 +4394,8 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
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if (TI->getNumSuccessors())
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SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
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// Check successor nodes PHI nodes that expect a constant to be available from
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// this block.
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// Check successor nodes' PHI nodes that expect a constant to be available
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// from this block.
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for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
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BasicBlock *SuccBB = TI->getSuccessor(succ);
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if (!isa<PHINode>(SuccBB->begin())) continue;
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@ -1774,9 +1774,9 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
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case MVT::Other: break;
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case MVT::i32:
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if (Op.Val->getValueType(1) == MVT::i32) {
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Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
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Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
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ResultVals[0] = Chain.getValue(0);
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Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
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Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
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Chain.getValue(2)).getValue(1);
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ResultVals[1] = Chain.getValue(0);
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NumResults = 2;
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13
test/CodeGen/PowerPC/big-endian-call-result.ll
Normal file
13
test/CodeGen/PowerPC/big-endian-call-result.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
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; RUN: grep {addic 4, 4, 1}
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; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \
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; RUN: grep {addze 3, 3}
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declare i64 @foo();
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define i64 @bar()
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{
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%t = call i64 @foo()
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%s = add i64 %t, 1
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ret i64 %s
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}
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