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update a couple of references to SSARegMap.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45468 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-12-31 04:16:08 +00:00
parent 84bc5427d6
commit 534bcfb270
3 changed files with 7 additions and 8 deletions
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9
docs/CodeGenerator.html
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@ -719,8 +719,7 @@ comes from.</p>
corresponds one-to-one with the LLVM function input to the instruction selector.
In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
live out registers for the function. See
<tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>. See
<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
</div>
@ -1313,8 +1312,8 @@ bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
unsigned p_reg) {
assert(MRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
"Target register must be physical");
const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
return trc->contains(p_reg);
const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
return trc-&gt;contains(p_reg);
}
</pre>
</div>
@ -1343,7 +1342,7 @@ register. Whereas physical registers are statically defined in a
<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
application developer, that is not the case with virtual registers.
In order to create new virtual registers, use the method
<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
<tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
virtual register with the highest code.
</p>

2
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -606,7 +606,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
}
// TODO: Add tracking info to SSARegMap of which vregs are subregs
// TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
// to allow coalescing in the allocator
// If the node is only used by a CopyToReg and the dest reg is a vreg, use

4
lib/CodeGen/SimpleRegisterCoalescing.cpp
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@ -1410,8 +1410,8 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
(*I)->eraseFromParent();
}
// Transfer sub-registers info to SSARegMap now that coalescing information
// is complete.
// Transfer sub-registers info to MachineRegisterInfo now that coalescing
// information is complete.
RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1);
while (!SubRegIdxes.empty()) {
std::pair<unsigned, unsigned> RI = SubRegIdxes.back();