From 534bcfb270d25d2a29759d19981443fee7260e94 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 31 Dec 2007 04:16:08 +0000
Subject: [PATCH] update a couple of references to SSARegMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45468 91177308-0d34-0410-b5e6-96231b3b80d8
---
 docs/CodeGenerator.html                  | 9 ++++-----
 lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 2 +-
 lib/CodeGen/SimpleRegisterCoalescing.cpp | 4 ++--
 3 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index b5ffe1cc253..7be4689562b 100644
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -719,8 +719,7 @@ comes from.</p>
 corresponds one-to-one with the LLVM function input to the instruction selector.
 In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
 a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
-<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
-live out registers for the function.  See
+<tt>MachineFunctionInfo</tt>, and a <tt>MachineRegisterInfo</tt>.  See
 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
 
 </div>
@@ -1313,8 +1312,8 @@ bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
                                       unsigned p_reg) {
   assert(MRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
          "Target register must be physical");
-  const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
-  return trc->contains(p_reg);
+  const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
+  return trc-&gt;contains(p_reg);
 }
 </pre>
 </div>
@@ -1343,7 +1342,7 @@ register. Whereas physical registers are statically defined in a
 <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
 application developer, that is not the case with virtual registers.
 In order to create new virtual registers, use the method
-<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
+<tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method will return a
 virtual register with the highest code.
 </p>
 
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index ce0707423e6..f506b3ebfba 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -606,7 +606,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
       SubIdx = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
     }
     
-    // TODO: Add tracking info to SSARegMap of which vregs are subregs
+    // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs
     // to allow coalescing in the allocator
           
     // If the node is only used by a CopyToReg and the dest reg is a vreg, use
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index da8b39fb2d0..d48e1f9bafa 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1410,8 +1410,8 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
       (*I)->eraseFromParent();
     }
 
-    // Transfer sub-registers info to SSARegMap now that coalescing information
-    // is complete.
+    // Transfer sub-registers info to MachineRegisterInfo now that coalescing
+    // information is complete.
     RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1);
     while (!SubRegIdxes.empty()) {
       std::pair<unsigned, unsigned> RI = SubRegIdxes.back();