mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-24 08:33:39 +00:00
All that just to lower div and rem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25008 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
57030e36e4
commit
53d8970625
@ -206,16 +206,20 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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case AlphaISD::GlobalBaseReg:
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return getGlobalBaseReg();
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case ISD::TargetConstantPool: {
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Constant *C = cast<ConstantPoolSDNode>(N)->get();
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SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
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Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
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return CurDAG->SelectNodeTo(N, Alpha::LDAr, MVT::i64, CPI, Tmp);
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case AlphaISD::DivCall: {
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SDOperand Chain = CurDAG->getEntryNode();
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, Select(Op.getOperand(1)),
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SDOperand(0,0));
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Select(Op.getOperand(2)),
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Chain.getValue(1));
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Op.getOperand(0)),
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Chain.getValue(1));
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Chain = CurDAG->getTargetNode(Alpha::JSRsDAG, MVT::Other, MVT::Flag,
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Chain, Chain.getValue(1));
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
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Chain.getValue(1));
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return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
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}
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case ISD::ExternalSymbol:
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return CurDAG->SelectNodeTo(N, Alpha::LDQl, MVT::i64,
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CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(), MVT::i64),
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getGlobalBaseReg());
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case ISD::RET: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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@ -268,33 +272,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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}
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break;
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}
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::UREM:
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case ISD::SREM:
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if (MVT::isInteger(N->getValueType(0))) {
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const char* opstr = 0;
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switch(N->getOpcode()) {
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case ISD::UREM: opstr = "__remqu"; break;
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case ISD::SREM: opstr = "__remq"; break;
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case ISD::UDIV: opstr = "__divqu"; break;
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case ISD::SDIV: opstr = "__divq"; break;
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}
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SDOperand Tmp1 = Select(N->getOperand(0)),
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Tmp2 = Select(N->getOperand(1)),
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Addr = Select(CurDAG->getExternalSymbol(opstr,
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AlphaLowering.getPointerTy()));
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SDOperand Chain;
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Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Alpha::R24, Tmp1,
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SDOperand(0,0));
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Tmp2, Chain.getValue(1));
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, Chain.getValue(1));
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Chain = CurDAG->getTargetNode(Alpha::JSRsDAG, MVT::Other, MVT::Flag,
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Chain, Chain.getValue(1));
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return CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
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Chain.getValue(1));
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}
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break;
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case ISD::SETCC:
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if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
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@ -82,9 +82,10 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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}
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//If this didn't legalize into a div....
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// setOperationAction(ISD::SREM , MVT::i64, Expand);
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// setOperationAction(ISD::UREM , MVT::i64, Expand);
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setOperationAction(ISD::SREM , MVT::i64, Custom);
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setOperationAction(ISD::UREM , MVT::i64, Custom);
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setOperationAction(ISD::SDIV , MVT::i64, Custom);
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setOperationAction(ISD::UDIV , MVT::i64, Custom);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::MEMSET , MVT::Other, Expand);
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@ -104,10 +105,12 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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// We want to legalize GlobalAddress and ConstantPool and
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// ExternalSymbols nodes into the appropriate instructions to
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// materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
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addLegalFPImmediate(+0.0); //F31
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addLegalFPImmediate(-0.0); //-F31
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@ -461,6 +464,30 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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} else
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return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
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}
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case ISD::ExternalSymbol: {
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return DAG.getNode(AlphaISD::RelLit, MVT::i64,
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DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
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DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
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}
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::UREM:
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case ISD::SREM:
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if (MVT::isInteger(Op.getValueType())) {
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const char* opstr = 0;
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switch(Op.getOpcode()) {
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case ISD::UREM: opstr = "__remqu"; break;
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case ISD::SREM: opstr = "__remq"; break;
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case ISD::UDIV: opstr = "__divqu"; break;
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case ISD::SDIV: opstr = "__divq"; break;
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}
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SDOperand Tmp1 = Op.getOperand(0),
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Tmp2 = Op.getOperand(1),
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Addr = DAG.getExternalSymbol(opstr, MVT::i64);
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return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
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}
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break;
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}
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@ -35,9 +35,12 @@ namespace llvm {
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/// RetLit - Literal Relocation of a Global
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RelLit,
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/// GlobalBaseReg, used to restore the GOT ptr
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/// GlobalBaseReg - used to restore the GOT ptr
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GlobalBaseReg,
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/// DIVCALL - used for special library calls for div and rem
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DivCall,
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};
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}
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@ -74,7 +74,6 @@ class AlphaISel : public SelectionDAGISel {
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int count_ins;
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int count_outs;
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bool has_sym;
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int max_depth;
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public:
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@ -93,15 +92,12 @@ public:
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count_ins = 0;
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count_outs = 0;
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max_depth = 0;
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has_sym = false;
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// Codegen the basic block.
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ISelDAG = &DAG;
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max_depth = DAG.getRoot().getNodeDepth();
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Select(DAG.getRoot());
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if(has_sym)
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++count_ins;
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if(EnableAlphaCount)
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std::cerr << "COUNT: "
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<< BB->getParent()->getFunction ()->getName() << " "
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@ -689,12 +685,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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dyn_cast<ConstantPoolSDNode>(Address)) {
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unsigned CPIdx = BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get());
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has_sym = true;
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
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.addImm(getUID());
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BuildMI(BB, GetRelVersion(Opc), 2, Result)
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.addConstantPoolIndex(CPIdx).addReg(Tmp1);
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.addConstantPoolIndex(CPIdx).addReg(Hi);
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} else assert(0 && "Unknown Lo part");
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} else if(Address.getOpcode() == ISD::FrameIndex) {
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if (EnableAlphaLSMark)
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@ -717,56 +712,43 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R29).addReg(Alpha::R29);
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return Result;
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case AlphaISD::GPRelHi:
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case AlphaISD::GPRelHi: {
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unsigned hi = SelectExpr(N.getOperand(1));
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAHr, 2, Result)
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.addConstantPoolIndex(BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get()))
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.addReg(SelectExpr(N.getOperand(1)));
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getConstantPoolIndex(CP->get())).addReg(hi);
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else if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAHr, 2, Result)
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.addGlobalAddress(GASD->getGlobal())
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.addReg(SelectExpr(N.getOperand(1)));
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.addGlobalAddress(GASD->getGlobal()).addReg(hi);
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else assert(0 && "unknown Hi part");
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return Result;
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case AlphaISD::GPRelLo:
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}
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case AlphaISD::GPRelLo: {
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unsigned hi = SelectExpr(N.getOperand(1));
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if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAr, 2, Result)
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.addConstantPoolIndex(BB->getParent()->getConstantPool()->
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getConstantPoolIndex(CP->get()))
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.addReg(SelectExpr(N.getOperand(1)));
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getConstantPoolIndex(CP->get())).addReg(hi);
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else if (GlobalAddressSDNode *GASD =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDAr, 2, Result)
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.addGlobalAddress(GASD->getGlobal())
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.addReg(SelectExpr(N.getOperand(1)));
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.addGlobalAddress(GASD->getGlobal()).addReg(hi);
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else assert(0 && "unknown Lo part");
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return Result;
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}
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case AlphaISD::RelLit: {
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GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N.getOperand(0));
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BuildMI(BB, Alpha::LDQl, 2, Result)
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.addGlobalAddress(GASD->getGlobal())
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.addReg(SelectExpr(N.getOperand(1)));
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unsigned hi = SelectExpr(N.getOperand(1));
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if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDQl, 2, Result)
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.addGlobalAddress(GASD->getGlobal()).addReg(hi);
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else if (ExternalSymbolSDNode *ESSD = dyn_cast<ExternalSymbolSDNode>(N.getOperand(0)))
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BuildMI(BB, Alpha::LDQl, 2, Result)
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.addExternalSymbol(ESSD->getSymbol()).addReg(hi);
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return Result;
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}
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case ISD::ExternalSymbol:
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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Reg = Result = MakeReg(MVT::i64);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
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.addImm(getUID());
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BuildMI(BB, Alpha::LDQl, 2, Result)
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.addExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol())
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.addReg(Alpha::R29);
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return Result;
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case ISD::TAILCALL:
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case ISD::CALL:
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{
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@ -1248,60 +1230,16 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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case ISD::SDIV:
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{
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//check if we can convert into a shift!
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if (isSIntImmediate(N.getOperand(1), SImm) &&
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SImm != 0 && isPowerOf2_64(llabs(SImm))) {
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unsigned k = Log2_64(llabs(SImm));
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Tmp1 = SelectExpr(N.getOperand(0));
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if (k == 1)
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Tmp2 = Tmp1;
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else
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{
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Tmp2 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::SRAi, 2, Tmp2).addReg(Tmp1).addImm(k - 1);
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}
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Tmp3 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::SRLi, 2, Tmp3).addReg(Tmp2).addImm(64-k);
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unsigned Tmp4 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::ADDQ, 2, Tmp4).addReg(Tmp3).addReg(Tmp1);
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if (SImm > 0)
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BuildMI(BB, Alpha::SRAi, 2, Result).addReg(Tmp4).addImm(k);
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else
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{
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unsigned Tmp5 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::SRAi, 2, Tmp5).addReg(Tmp4).addImm(k);
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BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::R31).addReg(Tmp5);
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}
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return Result;
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}
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}
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//Else fall through
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case ISD::UDIV:
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//else fall though
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case ISD::UREM:
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case ISD::SREM: {
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const char* opstr = 0;
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switch(opcode) {
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case ISD::UREM: opstr = "__remqu"; break;
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case ISD::SREM: opstr = "__remq"; break;
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case ISD::UDIV: opstr = "__divqu"; break;
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case ISD::SDIV: opstr = "__divq"; break;
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}
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case AlphaISD::DivCall:
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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SDOperand Addr =
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ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
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Tmp3 = SelectExpr(Addr);
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//set up regs explicitly (helps Reg alloc)
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BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
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BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp3).addReg(Tmp3);
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Tmp3 = SelectExpr(N.getOperand(2));
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BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp2).addReg(Tmp2);
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BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp3).addReg(Tmp3);
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BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0);
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
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return Result;
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}
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case ISD::SELECT:
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if (isFP) {
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@ -1492,7 +1430,6 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
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unsigned CPI = CP->getConstantPoolIndex(C);
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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Tmp1 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI)
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.addReg(Alpha::R29);
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@ -434,6 +434,7 @@ let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
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let isCall = 1, Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
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def JSRsDAG : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0">; //Jump to div or rem
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def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return
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def BR : BForm<0x30, "br $RA,$DISP">; //Branch
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@ -575,9 +576,11 @@ def LDAHg : MFormAlt<0x09, "ldah $RA,0($RB)\t\t!gpdisp!$NUM">; //Load address
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}
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//Load quad, rellocated literal form
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let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
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let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
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def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
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[(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))]>;
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def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
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(LDQl texternalsym:$ext, GPRC:$RB)>;
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//Branches, int
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def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
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