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ARM: update peephole optimization.

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More condition codes are included when deciding whether to remove cmp after
a sub instruction. Specifically, we extend from GE|LT|GT|LE to 
GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we
should be able to replace with "sub a, b; movls".

rdar: 11725965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren 2012-06-25 21:49:38 +00:00
parent 2c5fbb9bcb
commit 540cda34b0
2 changed files with 30 additions and 2 deletions
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20
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1875,7 +1875,9 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
} }
// Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1). // Check whether the current instruction is SUB(r1, r2) or SUB(r2, r1).
if (SrcReg2 != 0 && Instr.getOpcode() == ARM::SUBrr && if (SrcReg2 != 0 &&
(Instr.getOpcode() == ARM::SUBrr ||
Instr.getOpcode() == ARM::t2SUBrr) &&
((Instr.getOperand(1).getReg() == SrcReg && ((Instr.getOperand(1).getReg() == SrcReg &&
Instr.getOperand(2).getReg() == SrcReg2) || Instr.getOperand(2).getReg() == SrcReg2) ||
(Instr.getOperand(1).getReg() == SrcReg2 && (Instr.getOperand(1).getReg() == SrcReg2 &&
@ -1976,6 +1978,12 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
case ARMCC::LT: case ARMCC::LT:
case ARMCC::GT: case ARMCC::GT:
case ARMCC::LE: case ARMCC::LE:
case ARMCC::HS:
case ARMCC::LS:
case ARMCC::HI:
case ARMCC::LO:
case ARMCC::EQ:
case ARMCC::NE:
// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
// on CMP needs to be updated to be based on SUB. // on CMP needs to be updated to be based on SUB.
// Push the condition code operands to OperandsToUpdate. // Push the condition code operands to OperandsToUpdate.
@ -2023,7 +2031,15 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
case ARMCC::GE: NewCC = ARMCC::LE; break; case ARMCC::GE: NewCC = ARMCC::LE; break;
case ARMCC::LT: NewCC = ARMCC::GT; break; case ARMCC::LT: NewCC = ARMCC::GT; break;
case ARMCC::GT: NewCC = ARMCC::LT; break; case ARMCC::GT: NewCC = ARMCC::LT; break;
case ARMCC::LE: NewCC = ARMCC::GT; break; case ARMCC::LE: NewCC = ARMCC::GE; break;
case ARMCC::HS: NewCC = ARMCC::LS; break;
case ARMCC::LS: NewCC = ARMCC::HS; break;
case ARMCC::HI: NewCC = ARMCC::LO; break;
case ARMCC::LO: NewCC = ARMCC::HI; break;
case ARMCC::EQ:
case ARMCC::NE:
NewCC = CC;
break;
} }
OperandsToUpdate[i]->setImm(NewCC); OperandsToUpdate[i]->setImm(NewCC);
} }

12
test/CodeGen/ARM/sub-cmp-peephole.ll
View File

@ -32,3 +32,15 @@ entry:
%sub. = select i1 %cmp, i32 %sub, i32 %b %sub. = select i1 %cmp, i32 %sub, i32 %b
ret i32 %sub. ret i32 %sub.
} }
; rdar://11725965
define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK: i:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp ult i32 %a, %b
%sub = sub i32 %b, %a
%sub. = select i1 %cmp, i32 %sub, i32 0
ret i32 %sub.
}