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R600/SI: Make sure target flags are set on pseudo VOP3 instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211120 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-06-17 19:34:46 +00:00
parent 4a5916aca9
commit 540fe7f20e
2 changed files with 14 additions and 14 deletions
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26
lib/Target/R600/SIInstrFormats.td
View File

@@ -51,6 +51,16 @@ class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
let Size = 8; let Size = 8;
} }
class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
Enc64 <outs, ins, asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOP3 = 1;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scalar operations // Scalar operations
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -207,7 +217,7 @@ class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
} }
class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64 <outs, ins, asm, pattern> { VOP3Common <outs, ins, asm, pattern> {
bits<8> dst; bits<8> dst;
bits<2> src0_modifiers; bits<2> src0_modifiers;
@@ -233,16 +243,11 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
let Inst{61} = src0_modifiers{0}; let Inst{61} = src0_modifiers{0};
let Inst{62} = src1_modifiers{0}; let Inst{62} = src1_modifiers{0};
let Inst{63} = src2_modifiers{0}; let Inst{63} = src2_modifiers{0};
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOP3 = 1;
} }
class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64 <outs, ins, asm, pattern> { VOP3Common <outs, ins, asm, pattern> {
bits<8> dst; bits<8> dst;
bits<2> src0_modifiers; bits<2> src0_modifiers;
@@ -266,11 +271,6 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
let Inst{62} = src1_modifiers{0}; let Inst{62} = src1_modifiers{0};
let Inst{63} = src2_modifiers{0}; let Inst{63} = src2_modifiers{0};
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOP3 = 1;
} }
class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :

2
lib/Target/R600/SIInstrInfo.td
View File

@@ -266,7 +266,7 @@ class SIMCInstr <string pseudo, int subtarget> {
multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern, multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
string opName> { string opName> {
def "" : InstSI <outs, ins, "", pattern>, VOP <opName>, def "" : VOP3Common <outs, ins, "", pattern>, VOP <opName>,
SIMCInstr<OpName, SISubtarget.NONE> { SIMCInstr<OpName, SISubtarget.NONE> {
let isPseudo = 1; let isPseudo = 1;
} }