mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-09 11:25:55 +00:00
Add support for llvm.sqrt and sin/cos if unsafe math optimizations are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21631 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -26,6 +26,7 @@
|
|||||||
#include "llvm/CodeGen/SSARegMap.h"
|
#include "llvm/CodeGen/SSARegMap.h"
|
||||||
#include "llvm/Target/MRegisterInfo.h"
|
#include "llvm/Target/MRegisterInfo.h"
|
||||||
#include "llvm/Target/TargetMachine.h"
|
#include "llvm/Target/TargetMachine.h"
|
||||||
|
#include "llvm/Target/TargetOptions.h"
|
||||||
#include "llvm/Support/GetElementPtrTypeIterator.h"
|
#include "llvm/Support/GetElementPtrTypeIterator.h"
|
||||||
#include "llvm/Support/InstVisitor.h"
|
#include "llvm/Support/InstVisitor.h"
|
||||||
#include "llvm/ADT/Statistic.h"
|
#include "llvm/ADT/Statistic.h"
|
||||||
@@ -1744,6 +1745,25 @@ void X86ISel::visitCallInst(CallInst &CI) {
|
|||||||
BuildMI(BB, X86::FABS, 1, DestReg).addReg(op1Reg);
|
BuildMI(BB, X86::FABS, 1, DestReg).addReg(op1Reg);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
} else if (F->getName() == "sin" && UnsafeFPMath || F->getName() == "sinf") {
|
||||||
|
if (CI.getNumOperands() == 2 && // Basic sanity checks.
|
||||||
|
CI.getOperand(1)->getType()->isFloatingPoint() &&
|
||||||
|
CI.getType() == CI.getOperand(1)->getType()) {
|
||||||
|
unsigned op1Reg = getReg(CI.getOperand(1));
|
||||||
|
unsigned DestReg = getReg(CI);
|
||||||
|
BuildMI(BB, X86::FSIN, 1, DestReg).addReg(op1Reg);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (F->getName() == "cos" && UnsafeFPMath || F->getName() == "cosf") {
|
||||||
|
if (CI.getNumOperands() == 2 && // Basic sanity checks.
|
||||||
|
CI.getOperand(1)->getType()->isFloatingPoint() &&
|
||||||
|
CI.getType() == CI.getOperand(1)->getType()) {
|
||||||
|
unsigned op1Reg = getReg(CI.getOperand(1));
|
||||||
|
unsigned DestReg = getReg(CI);
|
||||||
|
BuildMI(BB, X86::FCOS, 1, DestReg).addReg(op1Reg);
|
||||||
|
return;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Emit a CALL instruction with PC-relative displacement.
|
// Emit a CALL instruction with PC-relative displacement.
|
||||||
@@ -1780,6 +1800,7 @@ void X86ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
|
|||||||
case Intrinsic::memcpy:
|
case Intrinsic::memcpy:
|
||||||
case Intrinsic::memset:
|
case Intrinsic::memset:
|
||||||
case Intrinsic::isunordered:
|
case Intrinsic::isunordered:
|
||||||
|
case Intrinsic::sqrt:
|
||||||
case Intrinsic::readport:
|
case Intrinsic::readport:
|
||||||
case Intrinsic::writeport:
|
case Intrinsic::writeport:
|
||||||
// We directly implement these intrinsics
|
// We directly implement these intrinsics
|
||||||
@@ -1860,6 +1881,12 @@ void X86ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
|
|||||||
BuildMI(BB, X86::SETPr, 0, TmpReg2);
|
BuildMI(BB, X86::SETPr, 0, TmpReg2);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
case Intrinsic::sqrt:
|
||||||
|
TmpReg1 = getReg(CI.getOperand(1));
|
||||||
|
TmpReg2 = getReg(CI);
|
||||||
|
BuildMI(BB, X86::FSQRT, 1, TmpReg2).addReg(TmpReg1);
|
||||||
|
return;
|
||||||
|
|
||||||
case Intrinsic::memcpy: {
|
case Intrinsic::memcpy: {
|
||||||
assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
|
assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
|
||||||
unsigned Align = 1;
|
unsigned Align = 1;
|
||||||
|
Reference in New Issue
Block a user