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https://github.com/c64scene-ar/llvm-6502.git
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[X86] Avoid introducing extra shuffles when lowering packed vector shifts.
When lowering a vector shift node, the backend checks if the shift count is a
shuffle with a splat mask. If so, then it introduces an extra dag node to
extract the splat value from the shuffle. The splat value is then used
to generate a shift count of a target specific shift.
However, if we know that the shift count is a splat shuffle, we can use the
splat index 'I' to extract the I-th element from the first shuffle operand.
The advantage is that the splat shuffle may become dead since we no longer
use it.
Example:
;;
define <4 x i32> @example(<4 x i32> %a, <4 x i32> %b) {
%c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
%shl = shl <4 x i32> %a, %c
ret <4 x i32> %shl
}
;;
Before this patch, llc generated the following code (-mattr=+avx):
vpshufd $0, %xmm1, %xmm1 # xmm1 = xmm1[0,0,0,0]
vpxor %xmm2, %xmm2
vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
vpslld %xmm1, %xmm0, %xmm0
retq
With this patch, the redundant splat operation is removed from the code.
vpxor %xmm2, %xmm2
vpblendw $3, %xmm1, %xmm2, %xmm1 # xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
vpslld %xmm1, %xmm0, %xmm0
retq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223461 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
1610d6e878
commit
54529ed1c4
@ -18444,30 +18444,27 @@ static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
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} else {
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if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
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Amt = Amt.getOperand(0);
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if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
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cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
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ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
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if (SVN && SVN->isSplat()) {
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unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
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SDValue InVec = Amt.getOperand(0);
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if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
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unsigned NumElts = InVec.getValueType().getVectorNumElements();
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unsigned i = 0;
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for (; i != NumElts; ++i) {
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SDValue Arg = InVec.getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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BaseShAmt = Arg;
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break;
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}
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assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
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"Unexpected shuffle index found!");
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BaseShAmt = InVec.getOperand(SplatIdx);
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} else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
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if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
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unsigned SplatIdx =
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cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
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if (C->getZExtValue() == SplatIdx)
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BaseShAmt = InVec.getOperand(1);
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}
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}
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if (!BaseShAmt.getNode())
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BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
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DAG.getIntPtrConstant(0));
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if (!BaseShAmt)
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// Avoid introducing an extract element from a shuffle.
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BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
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DAG.getIntPtrConstant(SplatIdx));
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}
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}
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160
test/CodeGen/X86/lower-vec-shift-2.ll
Normal file
160
test/CodeGen/X86/lower-vec-shift-2.ll
Normal file
@ -0,0 +1,160 @@
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s -check-prefix=SSE2
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s -check-prefix=AVX
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define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {
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; SSE2-LABEL: test1:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %eax
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; SSE2-NEXT: movzwl %ax, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psllw %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test1:
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; AVX: # BB#0
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; AVX-NEXT: vmovd %xmm1, %eax
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; AVX-NEXT: movzwl %ax, %eax
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; AVX-NEXT: vmovd %eax, %xmm1
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; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
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%shl = shl <8 x i16> %A, %vecinit14
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ret <8 x i16> %shl
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}
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define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test2:
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; SSE2: # BB#0
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; SSE2-NEXT: xorps %xmm2, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm2
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; SSE2-NEXT: pslld %xmm2, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test2:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
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; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%shl = shl <4 x i32> %A, %vecinit6
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ret <4 x i32> %shl
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}
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define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) {
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; SSE2-LABEL: test3:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %rax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psllq %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test3:
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; AVX: # BB#0
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; AVX-NEXT: vmovq %xmm1, %rax
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; AVX-NEXT: vmovd %eax, %xmm1
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; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
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%shl = shl <2 x i64> %A, %vecinit2
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ret <2 x i64> %shl
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}
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define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) {
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; SSE2-LABEL: test4:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %eax
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; SSE2-NEXT: movzwl %ax, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psrlw %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test4:
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; AVX: # BB#0
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; AVX-NEXT: vmovd %xmm1, %eax
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; AVX-NEXT: movzwl %ax, %eax
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; AVX-NEXT: vmovd %eax, %xmm1
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; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
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%shr = lshr <8 x i16> %A, %vecinit14
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ret <8 x i16> %shr
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}
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define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test5:
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; SSE2: # BB#0
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; SSE2-NEXT: xorps %xmm2, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm2
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; SSE2-NEXT: psrld %xmm2, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test5:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
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; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = lshr <4 x i32> %A, %vecinit6
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ret <4 x i32> %shr
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}
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define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) {
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; SSE2-LABEL: test6:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %rax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psrlq %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test6:
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; AVX: # BB#0
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; AVX-NEXT: vmovq %xmm1, %rax
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; AVX-NEXT: vmovd %eax, %xmm1
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; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
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%shr = lshr <2 x i64> %A, %vecinit2
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ret <2 x i64> %shr
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}
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define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) {
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; SSE2-LABEL: test7:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %eax
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; SSE2-NEXT: movzwl %ax, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psraw %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test7:
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; AVX: # BB#0
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; AVX-NEXT: vmovd %xmm1, %eax
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; AVX-NEXT: movzwl %ax, %eax
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; AVX-NEXT: vmovd %eax, %xmm1
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; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
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%shr = ashr <8 x i16> %A, %vecinit14
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ret <8 x i16> %shr
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}
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define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test8:
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; SSE2: # BB#0
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; SSE2-NEXT: xorps %xmm2, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm2
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; SSE2-NEXT: psrad %xmm2, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test8:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
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; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = ashr <4 x i32> %A, %vecinit6
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ret <4 x i32> %shr
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}
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@ -57,7 +57,7 @@ entry:
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define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
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entry:
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; CHECK-LABEL: shift3a:
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; CHECK: movzwl
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; CHECK: pextrw $6
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; CHECK: psllw
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%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
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%shl = shl <8 x i16> %val, %shamt
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