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Don't cache the instruction and register info from the TargetMachine, because

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the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2013-06-07 06:19:56 +00:00
parent 9eb856bc29
commit 54a56fad36
9 changed files with 25 additions and 19 deletions
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6
lib/Target/Hexagon/HexagonCallingConvLower.cpp
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@@ -27,12 +27,11 @@ Hexagon_CCState::Hexagon_CCState(CallingConv::ID CC, bool isVarArg,
const TargetMachine &tm,
SmallVector<CCValAssign, 16> &locs,
LLVMContext &c)
: CallingConv(CC), IsVarArg(isVarArg), TM(tm),
TRI(*TM.getRegisterInfo()), Locs(locs), Context(c) {
: CallingConv(CC), IsVarArg(isVarArg), TM(tm), Locs(locs), Context(c) {
// No stack is used.
StackOffset = 0;
UsedRegs.resize((TRI.getNumRegs()+31)/32);
UsedRegs.resize((TM.getRegisterInfo()->getNumRegs()+31)/32);
}
// HandleByVal - Allocate a stack slot large enough to pass an argument by
@@ -56,6 +55,7 @@ void Hexagon_CCState::HandleByVal(unsigned ValNo, EVT ValVT,
/// MarkAllocated - Mark a register and all of its aliases as allocated.
void Hexagon_CCState::MarkAllocated(unsigned Reg) {
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
UsedRegs[*AI/32] |= 1 << (*AI&31);
}