Add instruction encodings and disassembly for 1r instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

@@ -11,8 +11,11 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "XCore.h"
+#include "XCoreRegisterInfo.h"
 #include "llvm/MC/MCDisassembler.h"
 #include "llvm/MC/MCFixedLenDisassembler.h"
+#include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/MemoryObject.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -25,11 +28,12 @@ namespace {
 
 /// XCoreDisassembler - a disasembler class for XCore.
 class XCoreDisassembler : public MCDisassembler {
+  const MCRegisterInfo *RegInfo;
 public:
   /// Constructor     - Initializes the disassembler.
   ///
-  XCoreDisassembler(const MCSubtargetInfo &STI) :
-    MCDisassembler(STI) {}
+  XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
+    MCDisassembler(STI), RegInfo(Info) {}
 
   /// getInstruction - See MCDisassembler.
   virtual DecodeStatus getInstruction(MCInst &instr,
@@ -38,8 +42,50 @@ public:
                                       uint64_t address,
                                       raw_ostream &vStream,
                                       raw_ostream &cStream) const;
-};
 
+  const MCRegisterInfo *getRegInfo() const { return RegInfo; }
+};
+}
+
+static bool readInstruction16(const MemoryObject &region,
+                              uint64_t address,
+                              uint64_t &size,
+                              uint16_t &insn) {
+  uint8_t Bytes[4];
+
+  // We want to read exactly 2 Bytes of data.
+  if (region.readBytes(address, 2, Bytes, NULL) == -1) {
+    size = 0;
+    return false;
+  }
+  // Encoded as a little-endian 16-bit word in the stream.
+  insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
+  return true;
+}
+
+static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
+  const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
+  return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
+}
+
+
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
+                                              unsigned RegNo,
+                                              uint64_t Address,
+                                              const void *Decoder);
+
+#include "XCoreGenDisassemblerTables.inc"
+
+static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
+                                              unsigned RegNo,
+                                              uint64_t Address,
+                                              const void *Decoder)
+{
+  if (RegNo > 11)
+    return MCDisassembler::Fail;
+  unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  return MCDisassembler::Success;
 }
 
 MCDisassembler::DecodeStatus
@@ -49,6 +95,20 @@ XCoreDisassembler::getInstruction(MCInst &instr,
                                   uint64_t Address,
                                   raw_ostream &vStream,
                                   raw_ostream &cStream) const {
+  uint16_t low;
+
+  if (!readInstruction16(Region, Address, Size, low)) {
+    return Fail;
+  }
+
+  // Calling the auto-generated decoder function.
+  DecodeStatus Result = decodeInstruction(DecoderTable16, instr, low, Address,
+                             this, STI);
+  if (Result != Fail) {
+    Size = 2;
+    return Result;
+  }
+
   return Fail;
 }
 
@@ -58,7 +118,7 @@ namespace llvm {
 
 static MCDisassembler *createXCoreDisassembler(const Target &T,
                                                const MCSubtargetInfo &STI) {
-  return new XCoreDisassembler(STI);
+  return new XCoreDisassembler(STI, T.createMCRegInfo(""));
 }
 
 extern "C" void LLVMInitializeXCoreDisassembler() {