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[FastIsel][X86] Add support for lowering the first 8 floating-point arguments.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-06-11 23:10:58 +00:00
parent a876305231
commit 54f1326e1f
1 changed files with 36 additions and 19 deletions
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55
lib/Target/X86/X86FastISel.cpp
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@ -1896,31 +1896,39 @@ bool X86FastISel::FastLowerArguments() {
return false; return false;
// Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments. // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments.
unsigned GPRCnt = 0;
unsigned FPRCnt = 0;
unsigned Idx = 1; unsigned Idx = 1;
for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); for (auto const &Arg : F->args()) {
I != E; ++I, ++Idx) {
if (Idx > 6)
return false;
if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) || if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
F->getAttributes().hasAttribute(Idx, Attribute::InReg) || F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
F->getAttributes().hasAttribute(Idx, Attribute::StructRet) || F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
F->getAttributes().hasAttribute(Idx, Attribute::Nest)) F->getAttributes().hasAttribute(Idx, Attribute::Nest))
return false; return false;
Type *ArgTy = I->getType(); Type *ArgTy = Arg.getType();
if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
return false; return false;
EVT ArgVT = TLI.getValueType(ArgTy); EVT ArgVT = TLI.getValueType(ArgTy);
if (!ArgVT.isSimple()) return false; if (!ArgVT.isSimple()) return false;
switch (ArgVT.getSimpleVT().SimpleTy) { switch (ArgVT.getSimpleVT().SimpleTy) {
default: return false;
case MVT::i32: case MVT::i32:
case MVT::i64: case MVT::i64:
++GPRCnt;
break;
case MVT::f32:
case MVT::f64:
++FPRCnt;
break; break;
default:
return false;
} }
if (GPRCnt > 6)
return false;
if (FPRCnt > 8)
return false;
} }
static const MCPhysReg GPR32ArgRegs[] = { static const MCPhysReg GPR32ArgRegs[] = {
@ -1929,24 +1937,33 @@ bool X86FastISel::FastLowerArguments() {
static const MCPhysReg GPR64ArgRegs[] = { static const MCPhysReg GPR64ArgRegs[] = {
X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
}; };
static const MCPhysReg XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
};
Idx = 0; unsigned GPRIdx = 0;
const TargetRegisterClass *RC32 = TLI.getRegClassFor(MVT::i32); unsigned FPRIdx = 0;
const TargetRegisterClass *RC64 = TLI.getRegClassFor(MVT::i64); for (auto const &Arg : F->args()) {
for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); MVT VT = TLI.getSimpleValueType(Arg.getType());
I != E; ++I, ++Idx) { const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
bool is32Bit = TLI.getValueType(I->getType()) == MVT::i32; unsigned SrcReg;
const TargetRegisterClass *RC = is32Bit ? RC32 : RC64; switch (VT.SimpleTy) {
unsigned SrcReg = is32Bit ? GPR32ArgRegs[Idx] : GPR64ArgRegs[Idx]; default: llvm_unreachable("Unexpected value type.");
case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break;
case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break;
case MVT::f32: // fall-through
case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break;
}
unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
// FIXME: Unfortunately it's necessary to emit a copy from the livein copy. // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
// Without this, EmitLiveInCopies may eliminate the livein if its only // Without this, EmitLiveInCopies may eliminate the livein if its only
// use is a bitcast (which isn't turned into an instruction). // use is a bitcast (which isn't turned into an instruction).
unsigned ResultReg = createResultReg(RC); unsigned ResultReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), TII.get(TargetOpcode::COPY), ResultReg)
ResultReg).addReg(DstReg, getKillRegState(true)); .addReg(DstReg, getKillRegState(true));
UpdateValueMap(I, ResultReg); UpdateValueMap(&Arg, ResultReg);
} }
return true; return true;
} }